IDT82V2108PX8 IDT, Integrated Device Technology Inc, IDT82V2108PX8 Datasheet - Page 42

• Manufacturer Part Number: IDT82V2108PX8
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX8

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX8

IDT82V2108
Functional Description
RSCFS
RSCCK
RSFSn
RSDn
RSFSn
(The RSCKn is selected by the RSCKSEL (b5, E1-001H) to output a jitter attenuated 2.048MHz (i.e., smoothed LRCKn) or 8KHz
clock (smoothed LRCKn divided by 256).)
(The RSCKn is selected by the RSCKSEL (b5, E1-001H) to output a jitter attenuated 2.048MHz (i.e., smoothed LRCKn) or 8KHz
clock (smoothed LRCKn divided by 256).)
RSCFS
RSDn
RSDn
RSCCK
When the RSD_RSCFS_EDGE (b5, E1-014H) is logic 0:
When the RSD_RSCFS_EDGE (b5, E1-014H) is logic 1:
Figure 10. E1 Receive Clock Slave RSCK Reference Mode - Functional Timing Example 1
Figure 11. E1 Receive Clock Slave RSCK Reference Mode - Functional Timing Example 2
The DE (b4, E1-010H) is logic 0 and the FE (b3, E1-010H) is logic 0. The timeslot offset and the bit offset enable are both 0:
1
1
1
2
2
2
3
3
3
4
4
TS31
The CMS (b2, E1-010H) is logic 0, i.e., the backplane clock rate is 2.048Mbit/s.
TS31
4
5
The CMS (b2, E1-010H) is logic 1, i.e., the backplane clock rate is 4.096Mbit/s.
TS31
5
5
6
The DE (b4, E1-010H) is logic 0 and the FE (b3, E1-010H) is logic 1.
6
6
7
7
7
8
8
8
1
1
1
2
2
2
3
3
32
3
4
4
TS0
4
TS0
5
5
TS0
5
6
6
6
7
7
7
8
8
8
1
1
1
2
2
2
3
3
TS1
3
T1 / E1 / J1 OCTAL FRAMER
4
TS1
4
TS1
4
5
5
5
6
6
6
March 5, 2009