IDT82V2108PX8 IDT, Integrated Device Technology Inc, IDT82V2108PX8 Datasheet - Page 93

• Manufacturer Part Number: IDT82V2108PX8
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX8

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX8

IDT82V2108
the current entire HDLC frame is indicated by the EOM (b3, T1/J1-
034H). When it is set, the HDLC data should be transmitted even if it
does not exceed the upper threshold of the FIFO. The FCS, if enabled
by the CRC (b1, T1/J1-034H), will be added before the closing flag auto-
matically. Zero stuffing is automatically performed to the serial output
data when there are five consecutive ones in the HDLC data or in the
FCS. A 7F abort sequence which deactivates the current HDLC packet
can be inserted anytime the ABT (b2, T1/J1-034H) is set. When the ABT
(b2, T1/J1-034H) is set, the current byte in the TD[7:0] (b7~0, T1/J1-
039H) is still transmitted, and then the FIFO is cleared and the 7F abort
sequence is transmitted continuously. The low threshold of the FIFO can
be set in the LINT[6:0] (b6~0, T1/J1-036H), which should always be less
than the value of the UTHR[6:0] (b6~0, T1/J1-035H). The FIFO can be
cleared anytime the FIFOCLR (b6, T1/J1-034H) is set. Flags (7E) will
consecutively be transmitted when there is no HDLC data to be transmit-
ted during the data link activating.
setting in the LINT[6:0] (b6~0, T1/J1-036H), the BLFILL (b5, T1/J1-
038H) will be set for indication. A transition from logic 0 to 1 on the
BLFILL (b5, T1/J1-038H) will cause a logic 1 in the LFILLI (b0, T1/J1-
038H). The interrupt on the INT pin will occur when the LFILLE (b0, T1/
J1-037H) is enabled;
bytes, the FULL (b6, T1/J1-038H) will be set for indication. A transition
from logic 0 to 1 on the FULL (b6, T1/J1-038H) will cause a logic 1 in the
FULLI (b3, T1/J1-038H). The interrupt on the INT pin will occur when the
FULLE (b3, T1/J1-037H) is enabled;
data is still written to it, the FIFO will overflow and the OVRI (b2, T1/J1-
038H) will be set for indication. The interrupt on the INT pin will occur
when the OVRE (b2, T1/J1-037H) is enabled.
transmitted in the FIFO, the FIFO is underrun and the UDRI (b1, T1/J1-
038H) will be set for indication. The interrupt on the INT pin will occur
when the UDRE (b1, T1/J1-037H) is enabled.
Functional Description
Four interrupt sources can be derived from this block.
1. When the FIFO is empty or the data in the FIFO is less than the
2. When the data in the FIFO reaches its maximum capacity - 128
3. When the FIFO has been filled with 128 bytes already and new
4. When the transmission is in process and it is out of data to be
83
3.17
(TBOM) - T1/J1 ONLY
ESF format in T1/J1 mode. The standard of the BOM is defined in the
ANSI T1.403-1989. The Bit Oriented Message (BOM) of each framer
operates independently.
the F-bit in the ESF format (refer to Table 4). The six ‘X’s represent the
code that can be programmed in the BOC[5:0] (b5~0, T1/J1-05DH).
When the BOC[5:0] (b5~0, T1/J1-05DH) are written with the bits other
than the ‘111111’, they will occupy the six ‘X’s’ positions and the BOM will
be transmitted.
BOC[5:0] (b5~0, T1/J1-05DH), a BOM disabled pattern will be transmit-
ted automatically. In T1 mode, the pattern is ‘FFFF’. In J1 mode, the pat-
tern is ‘FF7E’. The disable pattern should be repeated 16 times before
the HDLC bits (refer to Chapter 3.16 HDLC Transmitter (THDLC)) are
inserted in the DL bit. The transmission of the BOM takes priority over
any other substitutions of the DL bit except for the Yellow alarm signal.
3.18
(IBCG) - T1/J1 ONLY
loopback code in a framed or unframed T1/J1 data stream. The Inband
Loopback Code Generator of each framer operates independently.
grammed in the CL[1:0] (b1~0, T1/J1-046H) and the IBC[7:0] (b7~0, T1/
J1-047H) respectively. The code can only be transmitted when the EN
(b7, T1/J1-046H) is enabled. In framed mode, which is configured by the
UF (b6, T1/J1-046H), the F-bit can be replaced by the Frame Alignment
Pattern, DL and CRC-6 which are set in the Frame Generator block and
the 24 channels are replaced with the inband loopback code. In un-
framed mode, which is configured by the UF (b6, T1/J1-046H), all 193
bits are replaced with the inband loopback code.
the UF (b6, T1/J1-046H) should be the same.
The Bit Oriented Message (BOM) can only be transmitted in the
The BOM pattern is ‘111111110XXXXXX0’ which occupies the DL of
If the BOM transmission is stopped by setting all ones in the
The Inband Loopback Code Generator can only transmit inband
The length and the content of the inband loopback code are pro-
It is recommended that the setting of the EN (b7, T1/J1-046H) and
BIT-ORIENTED
INBAND
LOOPBACK
MESSAGE
T1 / E1 / J1 OCTAL FRAMER
CODE
TRANSMITTER
GENERATOR
March 5, 2009