IDT82V2108PX8 IDT, Integrated Device Technology Inc, IDT82V2108PX8 Datasheet - Page 49

• Manufacturer Part Number: IDT82V2108PX8
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX8

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX8

IDT82V2108
3.11.1.3
receive data from all eight framers. The data from up to four framers is
byte-interleaved and output on one of the two multiplexed buses. The
multiplexed bus is chosen by the MRBS (b4, E1-001H). When the data
from four framers is output on one multiplexed bus, the sequence of the
data is arranged by setting the time slot offset TSOFF[6:0] (b6~0, E1-
is clocked by MRSCCK. The active edge of MRSCCK to sample the
pulse on MRSCFS and to update the data on MRSD, MRSFS and MRS-
SIG is determined by the following bits in the registers (refer to
Table 15).
Table 15: Active Edge Selection of MRSCCK (in E1 Receive
Multiplexed Mode)
System Common Clock (MRSCCK) is provided by the system side. It is
used as a common timing clock for all eight framers. The frequency of
RSCCK can be chosen by the CMS (b2, E1-010H) to be the same as
the bit rate of the received data stream (8.192Mb/s), or double the bit
Functional Description
Note:
If the setting in the FE (b3, E1-010H) and DE (b4, E1-010H) is different, MRSFS will be
one clock edge ahead of MRSD.
The FE (b3, E1-010H) and DE (b4, E1-010H) of all eight framers should be configured to
the same value.
There is a special case when the CMS (b2, E1-010H) is logic 1 and the DE (b4, E1-
010H) is equal to FE (b3, E1-010H). The RSD_RSCFS_EDGE (b5, E1-014H) is invalid
and the signals on the MRSD, MRSSIG and MRSFS pins are updated on the first active
edge of MRSCCK.
In this mode (refer to Figure 19), two multiplexed buses are used to
In the Receive Multiplexed mode, the Multiplexed Receive Side
In the Receive Multiplexed mode, the data on the system interface
MRSCFS
MRSSIG
MRSFS
MRSD
Receive Multiplexed Mode
MRSCCK
MRSCFS *
MRSD[1:2] *
MRSFS[1:2] *
MRSSIG[1:2] *
Note: * MRSCFS, MRSD, MRSFS, MRSSIG are timed to MRSCCK
the Bit Determining the Active Edge of MRSCCK
DE (b4, E1-010H)
FE (b3, E1-010H)
Interface
Receive
System
Figure 19. Receive Multiplexed Mode
The Other Four of the Framer #1~#8
Any Four of the Framer #1~#8
Elastic
Store
Processor
39
Frame
013H). The data from different framers on one multiplexed bus must be
shifted by a different time slot offset to avoid data mixing. Then the
received data of each framer can be controlled by the MRBC (b3, E1-
001H) to output to the selected multiplexed bus or not. The MRBC (b3,
E1-001H) of the framers that are output to the same multiplexed bus
must be set to the same value.
rate of the received data stream (16.384 Mb/s). If the frequency of
RSCCK is double the bit rate of the received data stream, there will be
two active edges in one bit time. In this case, the RSD_RSCFS_EDGE
(b5, E1-014H) determines the active edge to update the signals on the
MRSD, MRSSIG and MRSFS pins; however, the pulse on MRSCFS (if it
exists) is always sampled on its first active edge. However, if the CMS
(b2, E1-010H) or the RSD_RSCFS_EDGE (b5, E1-014H) of any of the
eight framers is configured as logic 1, all the others are taken as logic 1.
That is, the CMS (b2, E1-010H) and the RSD_RSCFS_EDGE (b5, E1-
014H) of the eight framers should be configured to the same value in the
Receive Multiplexed mode.
System Common Frame Pulse (MRSCFS) is used as a common framing
signal to align the data streams on the two multiplexed buses. MRSCFS
asserts on each first bit of Basic Frame of the selected first framer. The
valid polarity of MRSCFS is configured by the FPINV (b6, E1-011H). The
framing signals on MRSCFS will also be ignored by setting the
FPMODE (b5, E1-011H) to ‘0’. The FPINV (b6, E1-011H) and the
FPMODE (b5, E1-011H) of the eight framers should be set to the same
value.
8.192Mb/s.
PERTS_RSFS (b3, E1-00EH) and REF_MRSFS (b2, E1-00EH) to out-
put all zeros, to indicate the frame position or to output the same pulse
as MRSCFS. The PERTS_RSFS (b3, E1-00EH) and REF_MRSFS (b2,
E1-00EH) of the eight framers should be set to the same value. When it
is defined to indicate the frame position, MRSFS can only indicate the
first bit of a Basic Frame of the selected first framer no matter what is set
in the ROHM, BRXSMFP, BRXCMFP, ALTIFP (b3, b2, b1, b0, E1-011H).
Processor
Frame
In the Receive Multiplexed mode, the Multiplexed Receive Side
In the Receive Multiplexed mode, the bit rate on the MRSD pin is
In the Receive Multiplexed mode, MRSFS can be configured by the
Processor
Frame
FIFO
DPLL
DPLL
DPLL
FIFO
DPLL
FIFO
T1 / E1 / J1 OCTAL FRAMER
LRCK[1:8]
LRD[1:8]
March 5, 2009