IDT82V2108PX8 IDT, Integrated Device Technology Inc, IDT82V2108PX8 Datasheet - Page 164

• Manufacturer Part Number: IDT82V2108PX8
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX8

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX8

IDT82V2108
E1 RHDLC Receive Data Link 1 Control (TXCISEL = 0) (028H, 0A8H, 128H, 1A8H, 228H, 2A8H, 328H, 3A8H)
DL1_EVEN:
DL1_ODD:
TS16_EN:
DL1_TS[4:0]:
‘0’.
E1 RHDLC Data Link 1 Bit Select (TXCISEL = 0) (029H, 0A9H, 129H, 1A9H, 229H, 2A9H, 329H, 3A9H)
DL1_BITn:
Programming Information
Bit Name
Bit Name
Default
Default
Bit No.
Bit No.
Type
Type
When the TXCISEL (b3, E1-00AH) is ‘0’, this register is used for the Receive HDLC #1.
= 0: The data is not extracted from the even frames.
= 1: The data is extracted from the even frames.
The even frames are FAS frames.
= 0: The data is not extracted from the odd frames.
= 1: The data is extracted from the odd frames.
The odd frames are NFAS frames.
This bit is valid when the DL1_EVEN and DL1_ODD are both ‘0’.
= 0: The data is not extracted from TS16.
= 1: The data is extracted from TS16.
These bits represent the binary value of the time slot to extract the data from. They are invalid when the DL1_EVEN and the DL1_ODD are both
When the TXCISEL (b3, E1-00AH) is ‘0’, this register is used for the Receive HDLC #1.
= 0: The data is not extracted from the corresponding bit.
= 1: The data is extracted from the corresponding bit of the assigned time slot.
These bits are invalid when the DL1_EVEN and the DL1_ODD are both ‘0’.
The DL1_BIT[7] corresponds to the first bit (MSB) of the selected time slot.
DL1_EVEN
DL1_BIT[7]
R/W
R/W
7
0
7
0
DL1_BIT[6]
DL1_ODD
R/W
R/W
6
0
6
0
DL1_BIT[5]
TS16_EN
R/W
R/W
5
1
5
0
DL1_BIT[4]
DL1_TS[4]
R/W
R/W
4
0
4
0
154
DL1_BIT[3]
DL1_TS[3]
R/W
R/W
3
0
3
0
DL1_BIT[2]
DL1_TS[2]
R/W
R/W
2
0
2
0
T1 / E1 / J1 OCTAL FRAMER
DL1_BIT[1]
DL1_TS[1]
R/W
R/W
1
0
1
0
March 5, 2009
DL1_BIT[0]
DL1_TS[0]
R/W
R/W
0
0
0
0