IDT82V2108PX8 IDT, Integrated Device Technology Inc, IDT82V2108PX8 Datasheet - Page 91

• Manufacturer Part Number: IDT82V2108PX8
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX8

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX8

IDT82V2108
3.15.2
Frame (SF) or the Extended Super Frame (ESF) format. The selection is
made by the ESF (b4, T1/J1-044H).
and the FDIS (b3, T1/J1-006H) are logic 0, that is, the F-bit can be
replaced with the Frame Alignment Pattern, DL and CRC-6 (the DL and
CRC-6 bits only exist in the ESF format). Thus, the FAS can be replaced
in its position when the FBITBYP (b2, T1/J1-006H) is logic 0. In the SF
format, the Frame Alignment Pattern is ‘10001101110X’ and replaces
the F-bit of each frame input from the TSDn pin (refer to Table 3). In the
ESF format, the Frame Alignment Pattern is ‘001011’ and replaces the
F-bit in every 4th frame starting with Frame 4. The CRC-6 will replace
the F-bit in every 4th frame starting with Frame 2 if the CRCBYP (b1, T1/
J1-006H) is logic 0. The CRC-6 algorithm is chosen between the T1
standard and the J1 standard by the J1_CRC (b6, T1/J1-044H). The DL
bits will replace the F-bit in every other frame starting with Frame 1 when
the FDLBYP (b0, T1/J1-006H) is logic 0 (refer to Table 4).
(b7~6, T1/J1-TPLC-indirect registers - 31~48H) select the signaling bit
input from the TSDn pin to be replaced with the signaling input from the
TSSIGn pin, the signaling bit of all channels can be replaced with the
signaling of the 1st frame when the SIGAEN (b5, T1/J1-006H) is set.
This configuration is to avoid the signaling change in the middle of a SF/
ESF.
in the IDLE[7:0] (b7~0, T1/J1-TPLC-indirect registers - 19~30H) when
the MTRK (b7, T1/J1-044H) is set. When the MTRK (b7, T1/J1-044H) is
set, the signaling bits of all channels may also be replaced by the signal-
ing input from the TSSIGn pin or the data set in the A, B, C, D (b3~0, T1/
J1-TPLC-indirect registers - 31~48H) according to the setting in the
SIGC[1:0] (b7~6, T1/J1-TPLC-indirect registers - 31~48H). The MTRK
(b7, T1/J1-044H) takes effect only when the PCCE (b0, T1/J1-030H) in
the TPLC is logic 1.
be inserted in the 1st bit of each channel. The content of the mimic pat-
tern is the same as the F-bit. The mimic pattern insertion is for diagnos-
tic purposes.
transmitted when the XYEL (b2, T1/J1-045H) is enabled. The alarm sig-
Functional Description
Table 38: Interrupt Summary in E1 Mode
No.
1 The end of the first frame of a Signaling Multi-Frame is input to the Frame Generator when Signaling Multi-
2 The end of the first frame of a CRC-4 Multi-Frame is input to the Frame Generator when CRC Multi-Frame is
3 The end of the first frame of a CRC-4 Sub Multi-Frame is input to the Frame Generator when CRC Multi-Frame
4 The boundary of a FAS is input to the Frame Generator when Basic Frame is generated.
In T1/J1 mode, the data to be transmitted can be either the Super
The SF/ESF is generated on the base of the UF (b6, T1/J1-046H)
Before the data coming into the Frame Generator, if the SIGC[1:0]
The data input from the TSDn pin will be replaced by the code set
Configured by the TXMFP (b1, T1/J1-00AH), a mimic pattern can
The Yellow alarm signal can be inserted in the data stream to be
Frame is generated and coincides with the CRC Multi-Frame.
generated.
is generated.
T1/J1 MODE
Interrupt Sources
81
nal pattern is chosen between the T1 and J1 mode by the J1_YEL (b5,
T1/J1-044H). The pattern is:
nel.
ting the AUTOYELLOW (b3, T1/J1-000H) when Red alarm is declared in
the received data stream.
the XYEL (b2, T1/J1-045H) to be logic 0, a Yellow alarm disabled pattern
will be transmitted automatically. In T1 mode, the pattern is ‘FFFF’. In J1
mode, the pattern is ‘FF7E’. The disable pattern should be repeated 16
times before the BOC (refer to Chapter 3.17 Bit-Oriented Message
Transmitter (TBOM) - T1/J1 Only) or the HDLC bits (refer to
Chapter 3.16 HDLC Transmitter (THDLC)) are inserted in the DL bit.
The Yellow alarm takes the highest priority in these three kinds of inser-
tion.
TPLC insertion in the DL of the F-bit, the DL position will be forced to
transmit ‘FFFF’ in T1 mode or ‘7E7E’ in J1 mode continuously.
stream to be transmitted. The FIFO can be initiated by setting the
FRESH (b7, T1/J1-006H).
- In T1 SF format: Transmit the logic 0 on the 2nd bit of each chan-
- In J1 SF format: Transmit the logic 1 on the 12th F-bit.
- In T1 ESF format: Transmit the ‘FF00’ on each DL of F-bit.
- In J1 ESF format: Transmit the ‘FFFF’ on each DL of F-bit.
The Yellow alarm signal can also be inserted automatically by set-
In the ESF format, if the Yellow alarm signal is stopped by setting
If there are no Yellow alarm signal, no BOC, no HDLC bits or no
A FIFO is employed in the Frame Generator to store the data
SIGMFI(b4, E1-045H) SIGMFE(b4, E1-044H)
FASI (b3, E1-045H)
SMFI(b1, E1-045H)
MFI(b2, E1-045H)
Indication Bits
T1 / E1 / J1 OCTAL FRAMER
Interrupt Mask Bits
SMFE(b4, E1-044H)
FASE(b4, E1-044H)
MFE(b4, E1-044H)
March 5, 2009