ISP1181BDGG ST-Ericsson Inc, ISP1181BDGG Datasheet - Page 12

• Manufacturer Part Number: ISP1181BDGG
• Description: IC USB CNTRLR FULL-SPD 48-TSSOP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1181BDGG

• Controller Type: USB Peripheral Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 26mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1002-5; ISP1181BDGG,112

Philips Semiconductors
8. Modes of operation
Table 3:
9. Endpoint descriptions
9397 750 13958
Product data
Mode
0
1
2
3
Bus configuration modes
BUS_CONF[1:0]
0
0
1
1
9.1 Endpoint access
0
1
0
1
The ISP1181B has four bus configuration modes, selected via pins BUS_CONF1 and
BUS_CONF0:
Mode 0
Mode 1
Mode 2
Mode 3
The bus configurations for each of these modes are given in
circuits for each mode are given in
Each USB peripheral is logically composed of several independent endpoints. An
endpoint acts as a terminus of a communication flow between the host and the
peripheral. At design time each endpoint is assigned a unique number (endpoint
identifier, see
during enumeration), the endpoint number and the transfer direction allows each
endpoint to be uniquely referenced.
The ISP1181B has 16 endpoints: endpoint 0 (control IN and OUT) plus 14
configurable endpoints, which can be individually defined as
interrupt/bulk/isochronous, IN or OUT. Each enabled endpoint has an associated
FIFO, which can be accessed either via the parallel I/O interface or via DMA.
Table 4
I/O mode access. Endpoints 1 to 14 also support DMA access. FIFO DMA access is
selected and enabled via bits EPIDX[3:0] and DMAEN of the DMA Configuration
Register. A detailed description of the DMA operation is given in
PIO width
D[15:1], AD0
reserved
D[7:1], AD0
reserved
lists the endpoint access modes and programmability. All endpoints support
16-bit I/O port shared with 16-bit DMA port
reserved
8-bit I/O port shared with 8-bit DMA port
reserved.
Table
Rev. 02 — 07 December 2004
DMAWD = 0
-
reserved
D[7:1], AD0
reserved
4). The combination of the peripheral address (given by the host
DMA width
DMAWD = 1
D[15:1], AD0
reserved
-
reserved
Section
22.1.
Full-speed USB peripheral controller
Description
multiplexed address/data on pin AD0;
bus is shared by 16-bit I/O port and
16-bit DMA port
reserved
multiplexed address/data on pin AD0;
bus is shared by 8-bit I/O port and 8-bit
DMA port
reserved
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Table
ISP1181B
Section
3. Typical interface
10.
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