ISP1181BDGG ST-Ericsson Inc, ISP1181BDGG Datasheet - Page 17

• Manufacturer Part Number: ISP1181BDGG
• Description: IC USB CNTRLR FULL-SPD 48-TSSOP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1181BDGG

• Controller Type: USB Peripheral Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 26mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1002-5; ISP1181BDGG,112

Philips Semiconductors
9397 750 13958
Product data
10.2 8237 compatible mode
Table 7:
The 8237 compatible DMA mode is selected by clearing bit DAKOLY in the Hardware
Configuration Register (see
Table
Table 8:
The DMA subsystem of an IBM compatible PC is based on the Intel 8237 DMA
controller. It operates as a ‘fly-by’ DMA controller: the data is not stored in the DMA
controller, but it is transferred between an I/O port and a memory address. A typical
example of ISP1181B in 8237 compatible DMA mode is given in
The 8237 has two control signals for each DMA channel: DREQ (DMA Request) and
DACK (DMA Acknowledge). General control signals are HRQ (Hold Request) and
HLDA (Hold Acknowledge). The bus operation is controlled via MEMR (Memory
Read), MEMW (Memory Write), IOR (I/O read) and IOW (I/O write).
Symbol
DREQ
DACK
EOT
RD
WR
Fig 4. ISP1181B in 8237 compatible DMA mode.
Endpoint
identifier
8.
12
13
14
Endpoint selection for DMA transfer
8237 compatible mode: pin functions
DATA1 to DATA15
Description
DMA request
DMA acknowledge
end of transfer
read strobe
write strobe
ISP1181B
Rev. 02 — 07 December 2004
DREQ
DACK
AD0,
EPIDX[3:0]
WR
RD
1101
1110
1111
Table
20). The pin functions for this mode are shown in
RAM
I/O
O
I
I
I
I
MEMR
MEMW
DREQ
DACK
IOR
IOW
EPDIR = 0
OUT: read
OUT: read
OUT: read
CONTROLLER
Full-speed USB peripheral controller
…continued
Function
ISP1181B requests a DMA transfer
DMA controller confirms the transfer
DMA controller terminates the transfer
instructs ISP1181B to put data on the bus
instructs ISP1181B to get data from the
bus
DMA
8237
Transfer direction
HLDA
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
HRQ
ISP1181B
Figure
HRQ
HLDA
EPDIR = 1
CPU
004aaa137
IN: write
IN: write
IN: write
4.
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