ISP1181BDGG ST-Ericsson Inc, ISP1181BDGG Datasheet - Page 19

• Manufacturer Part Number: ISP1181BDGG
• Description: IC USB CNTRLR FULL-SPD 48-TSSOP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1181BDGG

• Controller Type: USB Peripheral Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 26mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1002-5; ISP1181BDGG,112

Philips Semiconductors
9397 750 13958
Product data
10.4.1 Bulk endpoints
10.4 End-Of-Transfer conditions
In DACK-only mode the ISP1181B uses the DACK signal as data strobe. Input
signals RD and WR are ignored. This mode is used in CPU systems that have a
single address space for memory and I/O access. Such systems have no separate
MEMW and MEMR signals: the RD and WR signals are also used as memory data
strobes.
A DMA transfer to/from a bulk endpoint can be terminated by any of the following
conditions (bit names refer to the DMA Configuration Register, see
External EOT:
DMA operation and clear any remaining data in the current FIFO. For a double-
buffered endpoint the other (inactive) buffer is not affected.
When writing to an IN endpoint, an EOT will stop the DMA operation and the data
packet in the FIFO (even if it is smaller than the maximum packet size) will be sent to
the USB host at the next IN token.
DMA Counter Register:
setting bit CNTREN in the DMA Configuration Register. The ISP1181B has a 16-bit
DMA Counter Register, which specifies the number of bytes to be transferred. When
DMA is enabled (DMAEN = 1), the internal DMA counter is loaded with the value from
the DMA Counter Register. When the internal counter completes the transfer as
programmed in the DMA counter, an EOT condition is generated and the DMA
operation stops.
•
•
•
•
Fig 5. ISP1181B in DACK-only DMA mode.
An external End-Of-Transfer signal occurs on input EOT
The DMA transfer completes as programmed in the DMA Counter register
(CNTREN = 1)
A short packet is received on an enabled OUT endpoint (SHORTP = 1)
DMA operation is disabled by clearing bit DMAEN.
DATA1 to DATA15
ISP1181B
When reading from an OUT endpoint, an external EOT will stop the
Rev. 02 — 07 December 2004
DREQ
DACK
AD0,
An EOT from the DMA Counter Register is enabled by
RAM
DREQ
DACK
RD
WR
CONTROLLER
Full-speed USB peripheral controller
DMA
HLDA
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
HRQ
ISP1181B
HRQ
HLDA
Table
CPU
004aaa138
24):
18 of 70