ISP1181BDGG ST-Ericsson Inc, ISP1181BDGG Datasheet - Page 34

• Manufacturer Part Number: ISP1181BDGG
• Description: IC USB CNTRLR FULL-SPD 48-TSSOP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1181BDGG

• Controller Type: USB Peripheral Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 26mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1002-5; ISP1181BDGG,112

Philips Semiconductors
9397 750 13958
Product data
12.2.2 Read Endpoint Status
Table 28:
Table 29:
Table 30:
Remark: There is no protection against writing or reading past a buffer’s boundary,
against writing into an OUT buffer or reading from an IN buffer. Any of these actions
could cause an incorrect operation. Data residing in an OUT buffer are only
meaningful after a successful transaction. Exception: during DMA access of a
double-buffered endpoint, the buffer pointer automatically points to the secondary
buffer after reaching the end of the primary buffer.
This command is used to read the status of an endpoint FIFO. The command
accesses the Endpoint Status Register, the bit allocation of which is shown in
Table
corresponding endpoint in the Interrupt Register (see
All bits of the Endpoint Status Register are read-only. Bit EPSTAL is controlled by the
Stall/Unstall commands and by the reception of a SETUP token (see
Code (Hex): 50 to 5F — read (control OUT, control IN, endpoint 1 to 14)
Byte #
(8-bit bus)
0
1
2
3
…
(N
A0
1
0
0
0
0
0
0
…
A0
1
0
0
0
…
1)
31. Reading the Endpoint Status Register will clear the interrupt bit set for the
Phase
command
data
data
data
data
data
data
…
Phase
command
data
data
data
…
Endpoint FIFO organization
Example of endpoint FIFO access (8-bit bus width)
Example of endpoint FIFO access (16-bit bus width)
Rev. 02 — 07 December 2004
Word #
(16-bit bus)
0 (lower byte)
0 (upper byte)
1 (lower byte)
1 (upper byte)
…
M = (N + 1) DIV 2
Bus lines
D[7:0]
D[7:0]
D[7:0]
D[7:0]
D[7:0]
D[7:0]
D[7:0]
…
Bus lines
D[7:0]
D[15:8]
D[15:0]
D[15:0]
D[15:0]
…
Byte #
-
0
1
2
3
4
5
…
Word #
-
-
0
1
2
…
Description
packet length (lower byte)
packet length (upper byte)
data byte 1
data byte 2
…
data byte N
Full-speed USB peripheral controller
Description
command code (00H to 1FH)
packet length (lower byte)
packet length (upper byte)
data byte 1
data byte 2
data byte 3
data byte 4
…
Description
command code (00H to 1FH)
ignored
packet length
data word 1 (data byte 2, data byte 1)
data word 2 (data byte 4, data byte 3)
…
Table
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
48).
ISP1181B
Section
12.2.3).
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