ISP1181BDGG ST-Ericsson Inc, ISP1181BDGG Datasheet - Page 27

• Manufacturer Part Number: ISP1181BDGG
• Description: IC USB CNTRLR FULL-SPD 48-TSSOP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1181BDGG

• Controller Type: USB Peripheral Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 26mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1002-5; ISP1181BDGG,112

Philips Semiconductors
Table 14:
Table 16:
9397 750 13958
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Endpoint Configuration Register: bit allocation
Address Register: bit allocation
FIFOEN
DEVEN
R/W
R/W
7
0
7
0
12.1.2 Write/Read Device Address
Remark: If any change is made to an endpoint configuration which affects the
allocated memory (size, enable/disable), the FIFO memory contents of all endpoints
becomes invalid. Therefore, all valid data must be removed from enabled endpoints
before changing the configuration.
Code (Hex): 20 to 2F — write (control OUT, control IN, endpoint 1 to 14)
Code (Hex): 30 to 3F — read (control OUT, control IN, endpoint 1 to 14)
Transaction — write/read 1 byte
Table 15:
This command is used to set the USB assigned address in the Address Register and
enable the USB device. The Address Register bit allocation is shown in
A USB bus reset sets the device address to 00H (internally) and enables the device.
The value of the Address Register (accessible by the micro) is not altered by the bus
reset. In response to the standard USB request Set Address the firmware must issue
a Write Device Address command, followed by sending an empty packet to the host.
The new device address is activated when the host acknowledges the empty packet.
Code (Hex): B6/B7 — write/read Address Register
Transaction — write/read 1 byte
Bit
7
6
5
4
3 to 0
EPDIR
R/W
R/W
6
0
6
0
Endpoint Configuration Register: bit description
Symbol
FIFOEN
EPDIR
DBLBUF
FFOISO
FFOSZ[3:0]
DBLBUF
R/W
R/W
5
0
5
0
Rev. 02 — 07 December 2004
FFOISO
Description
A logic 1 indicates an enabled FIFO with allocated memory.
A logic 0 indicates a disabled FIFO (no bytes allocated).
This bit defines the endpoint direction (0 = OUT, 1 = IN). It also
determines the DMA transfer direction (0 = read, 1 = write).
A logic 1 indicates that this endpoint has double buffering.
A logic 1 indicates an isochronous endpoint. A logic 0 indicates
a bulk or interrupt endpoint.
Selects the FIFO size according to
R/W
R/W
4
0
4
0
DEVADR[6:0]
R/W
R/W
3
0
3
0
Full-speed USB peripheral controller
R/W
R/W
2
0
2
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
FFOSZ[3:0]
Table 5
ISP1181B
R/W
R/W
1
0
1
0
Table
R/W
R/W
16.
0
0
0
0
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