ISP1181BDGG ST-Ericsson Inc, ISP1181BDGG Datasheet - Page 8

• Manufacturer Part Number: ISP1181BDGG
• Description: IC USB CNTRLR FULL-SPD 48-TSSOP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1181BDGG

• Controller Type: USB Peripheral Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 26mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1002-5; ISP1181BDGG,112

Philips Semiconductors
9397 750 13958
Product data
Table 2:
Symbol
DATA5
DATA4
DATA3
DATA2
DATA1
GND
V
AD0
A0
RD
WR
ALE
CS
RESET
CLKOUT
CC(3.3)
[1]
Pin description
Pin
TSSOP48
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
Rev. 02 — 07 December 2004
…continued
HVQFN48
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Type
I/O
I/O
I/O
I/O
I/O
-
-
I/O
I
I
I
I
I
I
O
Description
bit 5 of D[15:0]; bidirectional data line
(slew-rate controlled output, 4 mA)
bit 4 of D[15:0]; bidirectional data line
(slew-rate controlled output, 4 mA)
bit 3 of D[15:0]; bidirectional data line
(slew-rate controlled output, 4 mA)
bit 2 of D[15:0]; bidirectional data line
(slew-rate controlled output, 4 mA)
bit 1 of D[15:0]; bidirectional data line
(slew-rate controlled output, 4 mA)
ground supply
supply voltage (3.0 V to 3.6 V); leave this
pin unconnected when using V
multiplexed bidirectional address and data
line; represents address A0 or bit 0 of
D[15:0] in conjunction with input ALE;
level-sensitive input or slew-rate controlled
output (4 mA)
Address phase: a HIGH-to-LOW transition
on input ALE latches the level on this pin as
address A0 (1 = command, 0 = data)
Data phase: during reading this pin outputs
bit D[0]; during writing the level on this pin is
latched as bit D[0]
address input; selects command (A0 = 1) or
data (A0 = 0); in a multiplexed address/data
bus configuration this pin is not used and
must be tied LOW (connect to GND)
read strobe input
write strobe input
address latch enable input; a HIGH-to-LOW
transition latches the level on pin AD0 as
address information in a multiplexed
address/data bus configuration; must be
tied LOW (connect to GND) for a separate
address/data bus configuration
chip select input
reset input (Schmitt trigger); a LOW level
produces an asynchronous reset; connect
to V
circuit)
programmable clock output (2 mA)
Full-speed USB peripheral controller
CC
for power-on reset (internal POR
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
ISP1181B
CC
= 5.0 V
7 of 70