ISP1181BDGG ST-Ericsson Inc, ISP1181BDGG Datasheet - Page 36

• Manufacturer Part Number: ISP1181BDGG
• Description: IC USB CNTRLR FULL-SPD 48-TSSOP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1181BDGG

• Controller Type: USB Peripheral Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 26mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1002-5; ISP1181BDGG,112

Philips Semiconductors
Table 33:
9397 750 13958
Product data
Bit
Symbol
Reset
Access
Endpoint Status Image Register: bit allocation
EPSTAL
R
7
0
12.2.4 Validate Endpoint Buffer
12.2.5 Clear Endpoint Buffer
12.2.6 Check Endpoint Status
EPFULL1
This command signals the presence of valid data for transmission to the USB host, by
setting the Buffer Full flag of the selected IN endpoint. This indicates that the data in
the buffer is valid and can be sent to the host, when the next IN token is received. For
a double-buffered endpoint this command switches the current FIFO for CPU access.
Remark: For special aspects of the control IN endpoint see
Code (Hex): 61 to 6F — validate endpoint buffer (control IN, endpoint 1 to 14)
Transaction — none
This command unlocks and clears the buffer of the selected OUT endpoint, allowing
the reception of new packets. Reception of a complete packet causes the Buffer Full
flag of an OUT endpoint to be set. Any subsequent packets are refused by returning a
NAK condition, until the buffer is unlocked using this command. For a double-buffered
endpoint this command switches the current FIFO for CPU access.
Remark: For special aspects of the control OUT endpoint see
Code (Hex): 70, 72 to 7F — clear endpoint buffer (control OUT, endpoint 1 to 14)
Transaction — none
This command is used to check the status of the selected endpoint FIFO without
clearing any status or interrupt bits. The command accesses the Endpoint Status
Image Register, which contains a copy of the Endpoint Status Register. The bit
allocation of the Endpoint Status Image Register is shown in
Code (Hex): D0 to DF — check status (control OUT, control IN, endpoint 1 to 14)
Transaction — write/read 1 byte
Table 34:
Bit
7
6
5
4
R
6
0
Endpoint Status Image Register: bit description
Symbol
EPSTAL
EPFULL1
EPFULL0
DATA_PID
EPFULL0
R
5
0
Rev. 02 — 07 December 2004
DATA_PID
Description
This bit indicates whether the endpoint is stalled or not
(1 = stalled, 0 = not stalled).
A logic 1 indicates that the secondary endpoint buffer is full.
A logic 1 indicates that the primary endpoint buffer is full.
This bit indicates the data PID of the next packet
(0 = DATA0 PID, 1 = DATA1 PID).
R
4
0
WRITE
OVER
R
3
0
Full-speed USB peripheral controller
SETUPT
R
2
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Section
Table
CPUBUF
Section
ISP1181B
R
1
0
33.
9.5.
9.5.
reserved
R
0
0
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