FAN5071M Fairchild Semiconductor, FAN5071M Datasheet - Page 14

• Manufacturer Part Number: FAN5071M
• Description: DC/DC Switching Controllers DC/DC
• Manufacturer: Fairchild Semiconductor

Specifications of FAN5071M

• Number Of Outputs: 2
• Output Voltage: 1.05 V to 1.825 V
• Output Current: 28 A
• Input Voltage: 4.5 V to 5.25 V
• Mounting Style: SMD/SMT
• Package / Case: SOIC-24 Wide
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FAN5069 Rev. 1.1.5
© 2005 Fairchild Semiconductor Corporation
In the case of aluminum and polymer based capacitors,
the output capacitance is typically higher than normally
required to meet these requirements. While selecting the
ceramic capacitors for the output; although lower ESR
can be achieved easily, higher capacitance values are
required to meet the V
transient. From the stability point of view, the zero
caused by the ESR of the output capacitor plays an
important role in the stability of the converter.
Output Capacitor Selection (LDO)
For stable operation, the minimum capacitance of 100µF
with ESR around 100mΩ is recommended. For other val-
ues, contact the factory.
Power MOSFET Selection (PWM)
The FAN5069 is capable of driving N-Channel MOSFETs
as circuit switch elements. For better performance,
MOSFET selection must address these key parameters:
■
■
■
In typical applications for a buck converter, the duty
cycles are lower than 20%. To optimize the selection of
MOSFETs for both the high-side and low-side, follow dif-
ferent selection criteria. Select the high-side MOSFET to
minimize the switching losses and the low-side MOSFET
to minimize the conduction losses due to the channel
and the body diode losses. Note that the gate drive
losses also affect the temperature rise on the controller.
For loss calculation, refer to Fairchild's Application Note
AN-6005 and the associated spreadsheet.
High-Side Losses
Losses in the MOSFET can be understood by following
the switching interval of the MOSFET in Figure 22. MOS-
FET gate drive equivalent circuit is shown in Figure 23.
The maximum Drain-to-Source Voltage (V
be at least 25% higher than worst-case input voltage.
The MOSFETs should have low Q
The R
DS_ON
V
V
V
V
Figure 22. Switching Losses and Q
DS
I
SP
TH
GS
D
of the MOSFETs should be as low as possible.
t1
C
Q
ISS
GS
OUT(MIN)
t2
Q
G(SW)
C
Q
restrictions during a load
GD
GD
t3
G
, Q
GD,
t4
C
ISS
DS
and Q
) should
G
t5
4.5V
GS.
14
The upper graph in Figure 22 represents Drain-to-
Source Voltage (V
The lower graph details Gate-to-Source Voltage (V
vs. time with a constant current charging the gate. The x-
axis is representative of Gate Charge (Q
+ C
the current from the gate driver during t3 (as V
ing). Obtain the gate charge (Q
the lower graph from the MOSFET datasheets.
Assuming switching losses are about the same for both
the rising edge and falling edge, Q1's switching losses
occur during the shaded time when the MOSFET has
voltage across it and current through it.
Losses are given by (EQ. 10), (EQ. 11), and (EQ. 12):
P
where P
P
for a given MOSFET. R
temperature (T
fall time) and equals t2+t3 (Figure 22.).
The driver's impedance and C
period is controlled by the driver's impedance and Q
Since most of t
stant current for the driver to simplify the calculation of t
using the following equation:
Most MOSFET vendors specify Q
can be determined as:
Q
charge required to reach the MOSFET threshold (V
Note that for the high-side MOSFET, V
which can be as high as 20V in a typical portable appli-
cation. Include the power delivered to the MOSFET's
(P
the FAN5069.
P
P
t
s
UPPER
SW
G(SW)
SW
COND
GATE
=
GS
and P
Q
------------------- -
=
I
and it controls t1, t2, and t4 timing. C
Driver
) in calculating the power dissipation required for
G SW
= P
⎛
⎝
=
UPPER
= Q
(
V
---------------------
Figure 23. Drive Equivalent Circuit
5V
⎛
⎝
COND
DS
SW
V
--------------
)
R
GD
2
V
OUT
≈
D
×
IN
S
+ P
J
is the upper MOSFET's total losses and
--------------------------------------------- -
⎛
⎝
I
) and t
L
----------------------------------------
R
+ Q
are the switching and conduction losses
occurs when V
⎞
⎠
DS
×
Driver
COND
V
×
2 t
Q
) and Drain Current (I
CC
GS
I
OUT
×
2
G SW
DS(ON)
S
(
–
+
s
– Q
⎞ F
⎠
is the switching period (rise or
SW
HDRV
V
R
×
SP
)
Gate
SW
R
TH
DS ON
is at the maximum junction
ISS
G
GS
⎞
⎠
where Q
(
) parameters shown on
determine t2 while t3's
G
= V
GD
)
R
SP,
and Q
GATE
C
GS
G
DS
TH
assume a con-
C
D
). C
GD
www.fairchildsemi.com
) waveforms.
GD
equals V
GS
is the gate
ISS
DS
. Q
receives
(EQ. 10)
(EQ. 12)
(EQ. 13)
(EQ. 11)
VIN
= C
is fall-
G(SW)
TH
GD
GS
).
GD
IN
.
S
)
,