FAN5071M Fairchild Semiconductor, FAN5071M Datasheet - Page 15

• Manufacturer Part Number: FAN5071M
• Description: DC/DC Switching Controllers DC/DC
• Manufacturer: Fairchild Semiconductor

Specifications of FAN5071M

• Number Of Outputs: 2
• Output Voltage: 1.05 V to 1.825 V
• Output Current: 28 A
• Input Voltage: 4.5 V to 5.25 V
• Mounting Style: SMD/SMT
• Package / Case: SOIC-24 Wide
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FAN5069 Rev. 1.1.5
© 2005 Fairchild Semiconductor Corporation
P
where Q
Low-Side Losses
Q2 switches on or off with its parallel schottky diode
simultaneously conducting, so the V
P
negligible and Q2 is selected based on R
Conduction losses for Q2 are given by the equation:
where R
highest operating junction temperature and D=V
is the minimum duty cycle for the converter.
Since D
duces a conservative result, simplifying the calculation.
The maximum power dissipation (P
of the maximum allowable die temperature of the low-
side MOSFET, the θ
ambient temperature rise. P
the following equation:
θ
devoted to heat sinking.
Selection of MOSFET Snubber Circuit
The Switch node (SW) ringing is caused by fast switch-
ing transitions due to the energy stored in the parasitic
elements. This ringing on the SW node couples to other
circuits around the converter if they are not handled
properly. To dampen this ringing, an R-C snubber is con-
nected across the SW node and the source of the low-
side MOSFET.
P
P
P
JA
GATE
SW
Gate
COND
D MAX
(
depends primarily on the amount of PCB area
is proportional to V
is determined by the following equation:
=
MIN
)
G
=
DS(ON)
Q
=
V
is the total gate charge to reach V
(
IN
G
1 D
< 20% for portable computers, (1-D) ≈ 1 pro-
T
------------------------------------------------ -
×
–
J MAX
(
V
R
is the R
CC
) I
RAMP
×
)
θ
×
–
2
OUT
JA
F
JA,
T
SW
A MAX
DS(ON)
(
×
DS
and the maximum allowable
R
, Q2's switching losses are
DS ON
D(MAX)
)
Ramp
Generator
Figure 24. Closed-Loop System with Type-3 Network
(
of the MOSFET at the
)
D(MAX)
is calculated using
DS
DS(ON)
Amplifier
Summing
Current
Amplifier
≈ 0.5V. Since
Sense
) is a function
Σ
CC
.
alone.
(EQ. 14)
(EQ. 15)
(EQ. 16)
OUT
/V
DRIVER
IN
PWM
&
15
Reference
R-C components for the snubber are selected as follows:
a) Measure the SW node ringing frequency (F
b) Connect a capacitor (C
c) Place a resistor (R
d) Calculate the power dissipated in the snubber resistor
where, V
is the converter switching frequency.
The snubber resistor chosen should be de-rated to han-
dle the worst-case power dissipation. Do not use wire-
wound resistors for R
Loop Compensation
Typically, the closed loop crossover frequency (F
where the overall gain is unity, should be selected to
achieve optimal transient and steady-state response to
disturbances in line and load conditions. It is recom-
mended to keep F
quency of the converter. Higher phase margin tends to
have a more stable system with more sluggish response
to load transients. Optimum phase margin is about 60°, a
good compromise between steady state and transient
responses. A typical design should address variations
over a wide range of load conditions and over a large
sample of devices.
R
P
as shown in the following equation:
R SNUB
SNUB
low capacitance scope probe.
so that it reduces this ringing by half.
R
(
SNUB
=
IN(MAX)
is calculated using the following equation:
)
C1
---------------------------------------------- -
π
=
R
×
BIAS
C
V
F
IN
SNUB
ring
C2
is the maximum input voltage and FSW
Q2
R2
2
cross
×
L
Q1
×
C
SNUB
V
SNUB
SNUB
2
IN MAX
below fifth of the switching fre-
R
SNUB
(
DC
) in series with this capacitor.
C3
.
R1
R
)
) from SW node to GND
C
×
ES
R3
F
SW
R
V
L
OUT
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ring
(EQ. 17)
(EQ. 18)
) with a
cross
),