FDMS3615S Fairchild Semiconductor, FDMS3615S Datasheet
FDMS3615S
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FDMS3615S Summary of contents
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... Package Marking and Ordering Information Device Marking Device Y8OA FDMS3615S K10OC ©2011 Fairchild Semiconductor Corporation FDMS3615S Rev.C6 General Description This device includes two specialized N-Channel MOSFETs in a dual PQFN package. The switch node has been internally = connected to enable easy placement and routing of synchronous ...
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... Turn-Off Delay Time d(off) t Fall Time f Q Total Gate Charge g(TOT) Q Total Gate Charge g(TOT) Q Gate to Source Charge gs Q Gate to Drain “Miller” Charge gd ©2011 Fairchild Semiconductor Corporation FDMS3615S Rev. 25°C unless otherwise noted J Test Conditions = 250 μ mA 250 μA, referenced to 25° mA, referenced to 25° ...
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... Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0 N-ch device, the negative Vgs rating is for low duty cycle pulse ocurrence only. No continuous rating is implied based on starting N-ch 0.3 mH based on starting N-ch mH ©2011 Fairchild Semiconductor Corporation FDMS3615S Rev. 25°C unless otherwise noted J Test Conditions ...
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... JUNCTION TEMPERATURE ( , T J Figure 3. Normalized On Resistance vs Junction Temperature 45 μ PULSE DURATION = 80 s DUTY CYCLE = 0.5% MAX 150 GATE TO SOURCE VOLTAGE (V) GS Figure 5. Transfer Characteristics ©2011 Fairchild Semiconductor Corporation FDMS3615S Rev. 25°C unless otherwise noted μ 1.0 1 100 125 150 0 - 0.01 ...
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... Switching Capability 100 10 1 THIS AREA IS LIMITED SINGLE PULSE 0 MAX RATED 125 C/W θ 0.01 0.01 0 DRAIN to SOURCE VOLTAGE (V) DS Figure 11. Forward Bias Safe Operating Area ©2011 Fairchild Semiconductor Corporation FDMS3615S Rev. 25°C unless otherwise noted J 3000 1000 100 100 100 Figure 10 ...
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... Typical Characteristics (Q1 N-Channel) 2 DUTY CYCLE-DESCENDING ORDER 0.5 0.2 0.1 0.05 0.1 0.02 0.01 0.01 0.001 - Figure 13. ©2011 Fairchild Semiconductor Corporation FDMS3615S Rev. 25°C unless otherwise noted J SINGLE PULSE 125 C/W θ JA (Note 1b RECTANGULAR PULSE DURATION (sec) Junction-to-Ambient Transient Thermal Response Curve ...
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... PULSE DURATION = 80 s DUTY CYCLE = 0.5% MAX 150 1.0 1.5 2 GATE TO SOURCE VOLTAGE (V) GS Figure 18. Transfer Characteristics ©2011 Fairchild Semiconductor Corporation FDMS3615S Rev. °C unless otherwise noted μ s 1.0 1.5 Figure 15. Normalized on-Resistance vs Drain 50 75 100 125 150 0 - 0.01 0.001 2.5 3 ...
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... DS on SINGLE PULSE 0 MAX RATED 125 C/W θ 0.01 0.01 0 DRAIN to SOURCE VOLTAGE (V) DS Figure 24. Forward Bias Safe Operating Area ©2011 Fairchild Semiconductor Corporation FDMS3615S Rev. 25°C unless otherwise noted J 3000 1000 100 100 200 Figure 23. Maximum Continuous Drain 10000 1 ms ...
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... Typical Characteristics (Q2 N-Channel) 2 DUTY CYCLE-DESCENDING ORDER 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 0.001 0.0001 - Figure 26. Junction-to-Ambient Transient Thermal Response Curve ©2011 Fairchild Semiconductor Corporation FDMS3615S Rev. °C unless otherwise noted J SINGLE PULSE 125 C/W θ JA (Note 1b RECTANGULAR PULSE DURATION (sec ...
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... FDMS3615S di/dt = 300 100 TIME (ns) Figure 27. FDMS3615S SyncFET body diode reverse recovery characteristic ©2011 Fairchild Semiconductor Corporation FDMS3615S Rev.C6 (continued) Schottky barrier diodes exhibit significant leakage at high temperature and high reverse voltage. This will increase the power in the device μ ...
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... As shown in the figure 29, the Power Stage solution rings significantly less than competitor solutions under the same set of test conditions. Power Stage Device Figure 29. Power Stage phase node rising edge, High Side Turn on *Patent Pending ©2011 Fairchild Semiconductor Corporation FDMS3615S Rev.C6 Competitors solution 11 www.fairchildsemi.com ...
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... Power Stage is a high power density solution and all high current flow paths, such as VIN (D1), PHASE (S1/D2) and GND (S2), should be short and wide for better and stable current flow, heat radiation and system performance. A recommended layout proce- dure is discussed below to maximize the electrical and thermal performance of the part. ©2011 Fairchild Semiconductor Corporation FDMS3615S Rev.C6 Figure 31. Recommended PCB Layout 12 www.fairchildsemi.com ...
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... Vias should be relatively large, around 8 mils to 10 mils, and of reasonable inductance. Critical high frequency components such as ceramic bypass caps should be located close to the part and on the same side of the PCB. If not feasible, they should be connected from the backside via a network of low inductance vias. ©2011 Fairchild Semiconductor Corporation FDMS3615S Rev.C6 13 www.fairchildsemi.com ...
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... Dimensional Outline and Pad Layout 0. PKG PIN #1 IDENT MAY APPEAR AS OPTIONAL 0.35 6X 3.90 3.70 0.58 0.38 0.44 0.24 0.10 C 0.08 C 1.10 0.90 ©2011 Fairchild Semiconductor Corporation FDMS3615S Rev.C6 5.10 4.90 A PKG 0.63 6. 5.90 2.15 4.16 2.13 0. TOP VIEW 0.63 SEE DETAIL A ...
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... Definition of Terms Datasheet Identification Product Status Advance Information Formative / In Design Preliminary First Production No Identification Needed Full Production Obsolete Not In Production ©2011 Fairchild Semiconductor Corporation FDMS3615S Rev.C6 ® * PDP SPM™ Power-SPM™ ® PowerTrench PowerXS™ SM Programmable Active Droop™ ® QFET QS™ ...