A3P125-QNG132 MICROSEMI, A3P125-QNG132 Datasheet - Page 11

• Manufacturer Part Number: A3P125-QNG132
• Manufacturer: MICROSEMI

Specifications of A3P125-QNG132

• Lead Free Status / Rohs Status: Compliant

User Nonvolatile FlashROM
Actel Automotive ProASIC3 devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The
FlashROM can be used in diverse system applications:
The FlashROM is written using the standard Automotive ProASIC3 IEEE 1532 JTAG programming
interface.
The FlashROM can be programmed via the JTAG programming interface, and its contents can be read
back either through the JTAG programming interface or via direct FPGA core addressing. Note that the
FlashROM can only be programmed from the JTAG interface and cannot be programmed from the
internal logic array.
The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte
basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks
and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the
FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM
address define the byte.
The Actel Automotive ProASIC3 development software solutions, Libero
Environment (IDE) and Designer, have extensive support for the FlashROM. One such feature is auto-
generation of sequential programming files for applications requiring a unique serial number in each part.
Another feature allows the inclusion of static data for system version control. Data for the FlashROM can
be generated quickly and easily using Actel Libero IDE and Designer software tools. Comprehensive
programming file support is also included to allow for easy programming of large numbers of parts with
differing FlashROM contents.
SRAM
Automotive ProASIC3 devices have embedded SRAM blocks along their north and south sides. Each
variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18,
512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that can
be configured with different bit widths on each port. For example, data can be sent through a 4-bit port
and read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port
(ROM emulation mode) using the UJTAG macro.
PLL and CCC
Automotive ProASIC3 devices provide designers with very flexible clock conditioning circuit (CCC)
capabilities. Each member of the Automotive ProASIC3 family contains six CCCs. One CCC (center
west side) has a PLL.
The six CCC blocks are located at the four corners and the centers of the east and west sides. One CCC
(center west side) has a PLL.
All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay
operations as well as clock spine access.
The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs
located near the CCC that have dedicated connections to the CCC block.
The CCC block has these key features:
•
•
•
•
•
•
•
•
•
•
•
•
Unique protocol addressing (wireless or fixed)
System calibration settings
Device serialization and/or inventory control
Subscription-based business models (for example, infotainment systems)
Secure key storage for secure communications algorithms
Asset management/tracking
Date stamping
Version management
Wide input frequency range (f
Output frequency range (f
Clock delay adjustment via programmable and fixed delays from –7.56 ns to +11.12 ns
2 programmable delay types for clock skew minimization
OUT_CCC
IN_CCC
) = 0.75 MHz to 350 MHz
) = 1.5 MHz to 350 MHz
R e v i s i o n 1
Automotive ProASIC3 Flash Family FPGAs
®
Integrated Design
1 -5