A3P125-QNG132 MICROSEMI, A3P125-QNG132 Datasheet - Page 12

• Manufacturer Part Number: A3P125-QNG132
• Manufacturer: MICROSEMI

Specifications of A3P125-QNG132

• Lead Free Status / Rohs Status: Compliant

Automotive ProASIC3 Device Family Overview
1 - 6
Additional CCC specifications:
Global Clocking
Automotive ProASIC3 devices have extensive support for multiple clocking domains. In addition to the
CCC and PLL support described above, there is a comprehensive global clock distribution network.
Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant
global networks. The VersaNets can be driven by the CCC or directly accessed from the core via
multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid
distribution of high-fanout nets.
I/Os with Advanced I/O Standards
The Automotive ProASIC3 family of FPGAs features a flexible I/O structure, supporting a range of
voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V). Automotive ProASIC3 FPGAs support many different I/O
standards—single-ended and differential.
The I/Os are organized into banks, with two or four banks per device. The configuration of these banks
determines the I/O standards supported.
Each I/O module contains several input, output, and enable registers. These registers allow the
implementation of the following:
Automotive ProASIC3 banks for the A3P250 and A3P1000 devices support LVPECL, LVDS, B-LVDS,
and M-LVDS. B-LVDS and M-LVDS can support up to 20 loads.
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Clock frequency synthesis (for PLL only)
Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider
configuration (for PLL only).
Output duty cycle = 50% ± 1.5% or better (for PLL only)
Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global
network used (for PLL only)
Maximum acquisition time is 300 µs (for PLL only)
Low power consumption of 5 mW
Exceptional tolerance to input period jitter— allowable input jitter is up to 1.5 ns (for PLL only)
Four precise phases; maximum misalignment between adjacent phases of 40 ps × 350 MHz /
f
Single-Data-Rate applications
Double-Data-Rate applications—DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point
communications
OUT_CCC
(for PLL only)
R e vi s i o n 1