A3P125-QNG132 MICROSEMI, A3P125-QNG132 Datasheet - Page 61

• Manufacturer Part Number: A3P125-QNG132
• Manufacturer: MICROSEMI

Specifications of A3P125-QNG132

• Lead Free Status / Rohs Status: Compliant

Table 2-80 • 3.3 V PCI/PCI-X
Table 2-81 • 3.3 V PCI/PCI-X
Speed Grade
Std.
–1
Note:
Speed Grade
Std.
–1
Note:
For specific junction temperature and voltage supply levels, refer to
For specific junction temperature and voltage supply levels, refer to
Differential I/O Characteristics
Physical Implementation
Configuration of the I/O modules as a differential pair is handled by Actel Designer software when the
user instantiates a differential I/O macro in the design.
Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output
Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no
support for bidirectional I/Os or tristates with the LVPECL standards.
LVDS
Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It
requires that one data bit be carried through two signal lines, so two pins are needed. It also requires
external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in
page
macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for
the three driver resistors are different from those used in the LVPECL implementation because the output
standard specifications are different.
Along with LVDS I/O, ProASIC3 also supports Bus LVDS structure and Multipoint LVDS (M-LVDS)
configuration (up to 40 nodes).
Automotive-Case Conditions: T
Applicable to Advanced I/O Banks
Automotive-Case Conditions: T
Applicable to Standard Plus I/O Banks
2-50. The building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver
t
t
0.628
0.628
DOUT
0.53
DOUT
0.53
2.50
2.12
2.90
2.47
t
t
DP
DP
0.05
0.04
0.05
0.04
t
t
DIN
DIN
0.92
0.78
0.90
0.77
t
t
PY
PY
J
J
= 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
= 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
t
t
EOUT
0.45
0.38
EOUT
0.45
0.38
R e v i s i o n 1
1.23
1.23
1.23
1.23
t
t
ZL
ZL
0.91
0.91
0.91
0.91
t
t
ZH
ZH
Table 2-5 on page 2-5
Table 2-5 on page 2-5
Automotive ProASIC3 Flash Family FPGAs
3.02
2.57
3.02
2.57
t
t
LZ
LZ
3.48
2.96
3.48
2.96
t
t
HZ
HZ
2.40
2.41
2.40
2.41
t
t
ZLS
ZLS
for derating values.
for derating values.
t
t
2.11
2.11
2.11
2.11
Figure 2-12 on
ZHS
ZHS
Units
Units
ns
ns
ns
ns
2- 49