A3P125-QNG132 MICROSEMI, A3P125-QNG132 Datasheet - Page 15

• Manufacturer Part Number: A3P125-QNG132
• Manufacturer: MICROSEMI

Specifications of A3P125-QNG132

• Lead Free Status / Rohs Status: Compliant

Table 2-3 •
VCCI and
VMV
2.7 V or less
3 V
3.3 V
3.6 V
Notes:
1. The duration is allowed at one out of six clock cycles (estimated SSO density over cycles). If the overshoot/undershoot
2. This table refers only to overshoot/undershoot limits for simultaneously switching I/Os and does not provide PCI
occurs at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V.
overshoot/undershoot limits.
I/O Power-Up and Supply Voltage Thresholds for Power-On Reset
(Commercial and Industrial)
Sophisticated power-up management circuitry is designed into every ProASIC
ensure easy transition from the powered-off state to the powered-up state of the device. The many
different supplies can power up in any sequence with minimized current spikes or surges. In addition, the
I/O will be in a known state through the power-up sequence. The basic principle is shown in
on page
There are five regions to consider during power-up.
ProASIC3 I/Os are activated only if ALL of the following three conditions are met:
VCCI Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.2 V
Ramping down: 0.5 V < trip_point_down < 1.1 V
VCC Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.1 V
Ramping down: 0.5 V < trip_point_down < 1 V
VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically
built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following:
Internal Power-Up Activation Sequence
Overshoot and Undershoot Limits (as measured on quiet I/Os)
Average VCCI–GND Overshoot or Undershoot
1. VCC and VCCI are above the minimum specified trip points
2. VCCI > VCC – 0.75 V (typical)
3. Chip is in the operating mode.
•
•
1. Core
2. Input buffers
3. Output buffers, after 200 ns delay from input buffer activation
Duration as a Percentage of Clock Cycle
During programming, I/Os become tristated and weakly pulled up to V
JTAG supply, PLL power supplies, and charge pump V
behavior.
2-4.
10%
10%
10%
10%
5%
5%
5%
5%
R e v i s i o n 1
Maximum Overshoot/
Undershoot (115°C)
0.81 V
0.90 V
0.80 V
0.90 V
0.79 V
0.88 V
N/A
N/A
PUMP
Automotive ProASIC3 Flash Family FPGAs
(Figure 2-2 on page
supply have no influence on I/O
CCI
®
Maximum Overshoot/
.
3 device. These circuits
Undershoot (135°C)
2-4).
0.72 V
0.82 V
0.72 V
0.81 V
0.69 V
0.79 V
N/A
N/A
Figure 2-2
2 -3