A3P125-QNG132 MICROSEMI, A3P125-QNG132 Datasheet - Page 23

• Manufacturer Part Number: A3P125-QNG132
• Manufacturer: MICROSEMI

Specifications of A3P125-QNG132

• Lead Free Status / Rohs Status: Compliant

1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the
PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output
clock in the formula by adding its corresponding contribution (P
I/O Output Buffer Contribution—P
N
α
β
F
RAM Contribution—P
N
F
β
F
β
PLL Contribution—P
F
F
Guidelines
Toggle Rate Definition
A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the
toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are
some examples:
Enable Rate Definition
Output enable rate is the average percentage of time during which tristate outputs are enabled. When
nontristate output buffers are used, the enable rate should be 100%.
Table 2-12 • Toggle Rate Guidelines Recommended for Power Calculation
Component
α
α
CLK
READ-CLOCK
WRITE-CLOCK
CLKIN
CLKOUT
OUTPUTS
1
BLOCKS
2
3
2
1
2
is the I/O buffer enable rate—guidelines are provided in
is the RAM enable rate for read operations.
is the RAM enable rate for write operations—guidelines are provided in
is the I/O buffer toggle rate—guidelines are provided in
P
P
P
•
•
OUTPUTS
MEMORY
PLL
is the global clock signal frequency.
is the input clock frequency.
The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the
clock frequency.
The average toggle rate of an 8-bit counter is 25%:
– Bit 0 (LSB) = 100%
– Bit 1
– Bit 2
– …
– Bit 7 (MSB) = 0.78125%
– Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8
= P
is the output clock frequency.
is the number of RAM blocks used in the design.
is the number of I/O output buffers used in the design.
AC13
= P
is the memory read clock frequency.
= N
is the memory write clock frequency.
AC11
+ P
OUTPUTS
AC14
Toggle rate of VersaTile outputs
I/O buffer toggle rate
* N
= 50%
= 25%
PLL
BLOCKS
MEMORY
* F
*
α
CLKOUT
2
/ 2 *
* F
READ-CLOCK
β
1
1
* P
OUTPUTS
AC10
R e v i s i o n 1
* F
Definition
*
AC14
β
CLK
2
+ P
* F
CLKOUT
AC12
Table
Table 2-13 on page
* N
product) to the total PLL contribution.
2-12.
BLOCK
Automotive ProASIC3 Flash Family FPGAs
* F
WRITE-CLOCK
Table 2-13 on page
2-12.
*
β
Guideline
3
10%
10%
2-12.
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