A3P125-QNG132 MICROSEMI, A3P125-QNG132 Datasheet - Page 71

• Manufacturer Part Number: A3P125-QNG132
• Manufacturer: MICROSEMI

Specifications of A3P125-QNG132

• Lead Free Status / Rohs Status: Compliant

Figure 2-18 • Output Register Timing Diagram
Table 2-94 • Output Data Register Propagation Delays
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
Enable
Preset
DOUT
OCLKQ
OSUD
OHD
OSUE
OHE
OCLR2Q
OPRE2Q
OREMCLR
ORECCLR
OREMPRE
ORECPRE
OWCLR
OWPRE
OCKMPWH
OCKMPWL
CLK
Data_out
Clear
For specific junction temperature and voltage supply levels, refer to
Output Register
Timing Characteristics
Clock-to-Q of the Output Data Register
Data Setup Time for the Output Data Register
Data Hold Time for the Output Data Register
Enable Setup Time for the Output Data Register
Enable Hold Time for the Output Data Register
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Asynchronous Clear Minimum Pulse Width for the Output Data Register
Asynchronous Preset Minimum Pulse Width for the Output Data Register
Clock Minimum Pulse Width High for the Output Data Register
Clock Minimum Pulse Width Low for the Output Data Register
Automotive-Case Conditions: T
50%
50%
t
1
OSUE
t
OHE
50%
50%
t
OSUD
0
t
t
OHD
OCLKQ
50%
50%
J
Description
= 135°C, Worst-Case VCC = 1.425 V
50%
t
OWPRE
t
OPRE2Q
50%
50%
R e v i s i o n 1
t
ORECPRE
t
50%
OCLR2Q
50%
t
OWCLR
50%
50%
50%
Table 2-5 on page 2-5
t
ORECCLR
Automotive ProASIC3 Flash Family FPGAs
50%
t
OCKMPWH
t
50%
OREMPRE
for derating values.
t
50%
0.72 0.84
0.38 0.45
0.00 0.00
0.53 0.63
0.00 0.00
0.98 1.15
0.98 1.15
0.00 0.00
0.27 0.32
0.00 0.00
0.27 0.32
0.25 0.30
0.25 0.30
0.41 0.48
0.37 0.43
OCKMPWL
–1
Std. Units
t
OREMCLR
50%
50%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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