A3P125-QNG132 MICROSEMI, A3P125-QNG132 Datasheet - Page 69

• Manufacturer Part Number: A3P125-QNG132
• Manufacturer: MICROSEMI

Specifications of A3P125-QNG132

• Lead Free Status / Rohs Status: Compliant

Enable
Figure 2-17 • Input Register Timing Diagram
Table 2-92 • Input Data Register Propagation Delays
Data
Preset
Clear
Out_1
CLK
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
ICLKQ
ISUD
IHD
ISUE
IHE
ICLR2Q
IPRE2Q
IREMCLR
IRECCLR
IREMPRE
IRECPRE
IWCLR
IWPRE
ICKMPWH
ICKMPWL
For specific junction temperature and voltage supply levels, refer to
Input Register
Timing Characteristics
Automotive-Case Conditions: T
Clock-to-Q of the Input Data Register
Data Setup Time for the Input Data Register
Data Hold Time for the Input Data Register
Enable Setup Time for the Input Data Register
Enable Hold Time for the Input Data Register
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data Register
Asynchronous Preset Minimum Pulse Width for the Input Data Register
Clock Minimum Pulse Width High for the Input Data Register
Clock Minimum Pulse Width Low for the Input Data Register
50%
50%
t
1
ISUE
t
IHE
50%
50%
t
ISUD
0
t
ICLKQ
t
IHD
50%
50%
J
50%
Description
t
IWPRE
= 135°C, Worst-Case VCC = 1.425 V
t
IPRE2Q
50%
50%
t
R e v i s i o n 1
IRECPRE
50%
t
ICLR2Q
50%
t
IWCLR
50%
50%
50%
t
Table 2-5 on page 2-5
IRECCLR
Automotive ProASIC3 Flash Family FPGAs
50%
t
ICKMPWH
t
IREMPRE
50%
for derating values.
0.29 0.34
0.32 0.38
0.00 0.00
0.45 0.53
0.00 0.00
0.55 0.65
0.55 0.65
0.00 0.00
0.27 0.32
0.00 0.00
0.27 0.32
0.25 0.30
0.25 0.30
0.41 0.48
0.37 0.43
50%
t
–1
ICKMPWL
Std. Units
50%
t
50%
IREMCLR
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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