A3P125-QNG132 MICROSEMI, A3P125-QNG132 Datasheet - Page 85

• Manufacturer Part Number: A3P125-QNG132
• Manufacturer: MICROSEMI

Specifications of A3P125-QNG132

• Lead Free Status / Rohs Status: Compliant

Figure 2-27 • Timing Model and Waveforms
Table 2-106 • Register Delays
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
CLK
Data
EN
Out
PRE
CLKQ
SUD
HD
SUE
HE
CLR2Q
PRE2Q
REMCLR
RECCLR
REMPRE
RECPRE
WCLR
WPRE
CKMPWH
CKMPWL
CLR
For specific junction temperature and voltage supply levels, refer to
Timing Characteristics
Automotive-Case Conditions: T
Clock-to-Q of the Core Register
Data Setup Time for the Core Register
Data Hold Time for the Core Register
Enable Setup Time for the Core Register
Enable Hold Time for the Core Register
Asynchronous Clear-to-Q of the Core Register
Asynchronous Preset-to-Q of the Core Register
Asynchronous Clear Removal Time for the Core Register
Asynchronous Clear Recovery Time for the Core Register
Asynchronous Preset Removal Time for the Core Register
Asynchronous Preset Recovery Time for the Core Register
Asynchronous Clear Minimum Pulse Width for the Core Register
Asynchronous Preset Minimum Pulse Width for the Core Register
Clock Minimum Pulse Width High for the Core Register
Clock Minimum Pulse Width Low for the Core Register
50%
50%
t
SUE
t
HE
50%
t
CLKQ
50%
t
SUD
0
t
HD
t
PRE2Q
50%
50%
50%
J
t
WPRE
Description
= 135°C, Worst-Case VCC = 1.425 V
50%
50%
50%
t
t
RECPRE
WCLR
R e v i s i o n 1
50%
t
50%
50%
CLR2Q
50%
t
RECCLR
Table 2-5 on page 2-5
Automotive ProASIC3 Flash Family FPGAs
50%
t
CKMPWH
t
50%
REMPRE
0.67
0.52
0.00
0.55
0.00
0.49
0.49
0.00
0.27
0.00
0.27
0.25
0.25
0.41
0.37
for derating values.
t
CKMPWL
50%
–1
0.79
0.57
0.32
0.48
Std.
0.61
0.00
0.65
0.00
0.57
0.00
0.00
0.32
0.30
0.30
0.43
50%
50%
t
REMCLR
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2- 73