A3P125-QNG132 MICROSEMI, A3P125-QNG132 Datasheet - Page 77

• Manufacturer Part Number: A3P125-QNG132
• Manufacturer: MICROSEMI

Specifications of A3P125-QNG132

• Lead Free Status / Rohs Status: Compliant

Table 2-100 • Input DDR Propagation Delays
Parameter
t
t
t
t
t
t
t
t
t
t
t
F
Note:
DDRICLKQ1
DDRICLKQ2
DDRISUD
DDRIHD
DDRICLR2Q1
DDRICLR2Q2
DDRIREMCLR
DDRIRECCLR
DDRIWCLR
DDRICKMPWH
DDRICKMPWL
DDRIMAX
For specific junction temperature and voltage supply levels, refer to
Automotive-Case Conditions: T
Clock-to-Out Out_QR for Input DDR
Clock-to-Out Out_QF for Input DDR
Data Setup for Input DDR
Data Hold for Input DDR
Asynchronous Clear-to-Out Out_QR for Input DDR
Asynchronous Clear-to-Out Out_QF for Input DDR
Asynchronous Clear Removal Time for Input DDR
Asynchronous Clear Recovery Time for Input DDR
Asynchronous Clear Minimum Pulse Width for Input DDR
Clock Minimum Pulse Width High for Input DDR
Clock Minimum Pulse Width Low for Input DDR
Maximum Frequency for Input DDR
J
= 115°C, Worst-Case VCC = 1.425 V
Description
R e v i s i o n 1
Table 2-5 on page 2-5
Automotive ProASIC3 Flash Family FPGAs
0.33
0.46
0.34
0.00
0.55
0.68
0.00
0.27
0.25
0.41
0.37
TBD
–1
for derating values.
0.38
0.54
0.40
0.00
0.65
0.80
0.00
0.31
0.30
0.48
0.43
TBD
Std.
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2- 65