SC16C850VIBS,128 NXP Semiconductors, SC16C850VIBS,128 Datasheet - Page 18

• Manufacturer Part Number: SC16C850VIBS,128
• Description: IC UART SINGLE W/FIFO 32-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of SC16C850VIBS,128

• Features: Programmable
• Number Of Channels: 1, UART
• Fifo's: 128 Byte
• Protocol: RS485
• Voltage - Supply: 1.8V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN Exposed Pad
• Transmitter And Receiver Fifo Counter: Yes
• Data Rate: 5Mbps
• Mounting: Surface Mount
• Pin Count: 32
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935283087128; SC16C850VIBS-F; SC16C850VIBS-F

Table 7.
A3 A2 A1 Register
General Register Set
0
0
0
0
0
0
1
1
1
1
1
Special Register Set
0
0
Second Special Register Set
0
1
0
0
0
1
1
1
0
0
0
1
1
0
0
1
0
0
0
1
0
0
1
0
1
1
0
1
0
1
1
0
SC16C850V internal registers
RHR
THR
IER
FCR
ISR
LCR
MCR
LSR
EFCR
MSR
SPR
DLL
DLM
TXLVLCNT
RXLVLCNT
[4]
[2]
[5]
Default
XX
XX
00
00
01
00
00
60
00
X0
FF
XX
XX
00
00
[1]
Bit 7
bit 7
bit 7
CTS
interrupt
RCVR
trigger
(MSB)
FIFOs
enabled
divisor
latch
enable
clock
select
FIFO data
error
reserved
CD
bit 7
bit 7
bit 15
bit 7
bit 7
[3]
[3]
Bit 6
bit 6
bit 6
RTS
interrupt
RCVR
trigger
(LSB)
FIFOs
enabled
set break
IrDA
enable
THR and
TSR empty
reserved
RI
bit 6
bit 6
bit 14
bit 6
bit 6
[3]
Bit 5
bit 5
bit 5
Xoff
interrupt
TX trigger
(MSB)
INT priority
bit 4
set parity
INT type
THR empty break
reserved
DSR
bit 5
bit 5
bit 13
bit 5
bit 5
[3]
[3]
Bit 4
bit 4
bit 4
Sleep
mode
TX trigger
(LSB)
INT priority
bit 3
even parity parity enable
loopback
interrupt
reserved
CTS
bit 4
bit 4
bit 12
bit 4
bit 4
[3]
[3]
reserved
Bit 3
bit 3
bit 3
modem status
interrupt
reserved
INT priority
bit 2
OP2
framing error
ΔCD
bit 3
bit 3
bit 11
bit 3
bit 3
stop bits
Enable extra
Bit 2
bit 2
bit 2
receive line
status
interrupt
XMIT FIFO
reset
INT priority
bit 1
OP1
parity error
feature bit-1
ΔRI
bit 2
bit 2
bit 10
bit 2
bit 2
Bit 1
bit 1
bit 1
transmit
holding
register
interrupt
RCVR FIFO
reset
INT priority
bit 0
word length
bit 1
RTS
overrun error receive data
Enable extra
feature bit-0
ΔDSR
bit 1
bit 1
bit 9
bit 1
bit 1
Bit 0
bit 0
bit 0
receive
holding
register
FIFOs
enable
INT status
word length
bit 0
DTR
ready
Enable
TXLVLCNT/
RXLVLCNT
ΔCTS
bit 0
bit 0
bit 8
bit 0
bit 0
R/W
R
W
R/W
W
R
R/W
R/W
R
W
R
R/W
R/W
R/W
R
R