SC16C850VIBS,128 NXP Semiconductors, SC16C850VIBS,128 Datasheet - Page 9

• Manufacturer Part Number: SC16C850VIBS,128
• Description: IC UART SINGLE W/FIFO 32-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of SC16C850VIBS,128

• Features: Programmable
• Number Of Channels: 1, UART
• Fifo's: 128 Byte
• Protocol: RS485
• Voltage - Supply: 1.8V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN Exposed Pad
• Transmitter And Receiver Fifo Counter: Yes
• Data Rate: 5Mbps
• Mounting: Surface Mount
• Pin Count: 32
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935283087128; SC16C850VIBS-F; SC16C850VIBS-F

NXP Semiconductors
SC16C850V
Product data sheet
6.6 Software flow control
When AFCR1[2] is set to 1, then the function of CTS pin is mapped to the DSR pin, and
the function of RTS is mapped to DTR pin. DSR and DTR pins will behave as described
above for CTS and RTS.
With the automatic hardware flow control function enabled, an interrupt is generated when
the receive FIFO reaches the programmed trigger level. The RTS (or DTR) pin will not be
forced to a logic 1 (RTS off) until the receive FIFO reaches the next trigger level. However,
the RTS (or DTR) pin will return to a logic 0 after the receive buffer (FIFO) is unloaded to
the next trigger level below the programmed trigger level. Under the above described
conditions, the SC16C850V will continue to accept data until the receive FIFO is full.
When TXINTLVL, RXINTLVL, FLWCNTH and FLWCNTL in the First Extra Register Set
are all zeroes, the hardware and software flow control trigger levels are set by FCR[7:4];
see
When either TXINTLVL, RXINTLVL, FLWCNTH or FLWCNTL in the First Extra Register
Set contains any value other than 0x00, the hardware and software flow control trigger
levels are set by FLWCNTH and FLWCNTL. The content in FLWCNTH determines how
many bytes are in the receive FIFO before RTS (or DTR) is de-asserted or Xoff is sent.
The content of FLWCNTL determines how many bytes are in the receive FIFO before
RTS (or DTR) is asserted, or Xon is sent.
In 128-byte FIFO mode, hardware and software flow control trigger levels can be set to
any value between 1 and 128 in granularity of 1. The value of FLWCNTH should always
be greater than FLWCNTL. The UART does not check for this condition automatically, and
if this condition is not met spurious operation of the device might occur. When using
FLWCNTH and FWLCNTL, these registers must be initialized to the proper values before
hardware or software flow control is enabled via the EFR register.
When software flow control is enabled, the SC16C850V compares one or two sequentially
received data characters with the programmed Xon or Xoff character value(s). If the
received character(s) match the programmed Xoff values, the SC16C850V will halt
transmission (TX) as soon as the current character(s) has completed transmission. When
a match occurs, ISR bit 4 will be set (if enabled via IER[5]) and the interrupt output pin (if
receive interrupt is enabled) will be activated. Following a suspension due to a match of
the Xoff characters’ values, the SC16C850V will monitor the receive data stream for a
match to the Xon1/Xon2 character value(s). If a match is found, the SC16C850V will
resume operation and clear the flags (ISR[4]).
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0.
Following reset, the user can write any Xon/Xoff value desired for software flow control.
Different conditions can be set to detect Xon/Xoff characters and suspend/resume
transmissions (see
SC16C850V compares two consecutive receive characters with two software flow control
8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under
the above described flow control mechanisms, flow control characters are not placed
(stacked) in the receive FIFO. When using software flow control, the Xon/Xoff characters
cannot be used for data transfer.
Table
5.
Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
All information provided in this document is subject to legal disclaimers.
Table
Rev. 5 — 19 January 2011
24). When double 8-bit Xon/Xoff characters are selected, the
SC16C850V
© NXP B.V. 2011. All rights reserved.
9 of 48