SC16C850VIBS,128 NXP Semiconductors, SC16C850VIBS,128 Datasheet - Page 21

• Manufacturer Part Number: SC16C850VIBS,128
• Description: IC UART SINGLE W/FIFO 32-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of SC16C850VIBS,128

• Features: Programmable
• Number Of Channels: 1, UART
• Fifo's: 128 Byte
• Protocol: RS485
• Voltage - Supply: 1.8V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN Exposed Pad
• Transmitter And Receiver Fifo Counter: Yes
• Data Rate: 5Mbps
• Mounting: Surface Mount
• Pin Count: 32
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935283087128; SC16C850VIBS-F; SC16C850VIBS-F

NXP Semiconductors
SC16C850V
Product data sheet
7.2.1 IER versus transmit/receive FIFO interrupt mode operation
7.2.2 IER versus receive/transmit FIFO polled mode operation
Table 8.
When the receive FIFO is enabled (FCR[0] = logic 1), and receive interrupts
(IER[0] = logic 1) are enabled, the receive interrupts and register status will reflect the
following:
When FCR[0] = logic 1, setting IER[3:0] = zeroes puts the SC16C850V in the FIFO polled
mode of operation. In this mode, interrupts are not generated and the user must poll the
LSR register for TX and/or RX data status. Since the receiver and transmitter have
separate bits in the LSR either or both can be used in the polled mode by selecting
respective transmit or receive control bit(s).
Bit
1
0
•
•
•
•
•
•
•
•
•
The receive RXRDY interrupt (Level 2 ISR interrupt) is issued to the external CPU
when the receive FIFO has reached the programmed trigger level. It will be cleared
when the receive FIFO drops below the programmed trigger level.
Receive FIFO status will also be reflected in the user accessible ISR register when
the receive FIFO trigger level is reached. Both the ISR register receive status bit and
the interrupt will be cleared when the FIFO drops below the trigger level.
The receive data ready bit (LSR[0]) is set as soon as a character is transferred from
the shift register (RSR) to the receive FIFO. It is reset when the FIFO is empty.
When the Transmit FIFO and interrupts are enabled, an interrupt is generated when
the transmit FIFO is empty due to the unloading of the data by the TSR and UART for
transmission via the transmission media. The interrupt is cleared either by reading the
ISR, or by loading the THR with new data characters.
LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.
LSR[4:1] will provide the type of receive errors, or a receive break, if encountered.
LSR[5] will indicate when the transmit FIFO is empty.
LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty.
LSR[7] will show if any FIFO data errors occurred.
Symbol Description
IER[1]
IER[0]
Interrupt Enable Register bits description
Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
All information provided in this document is subject to legal disclaimers.
Transmit Holding Register interrupt. In the non-FIFO mode, this interrupt will be
issued whenever the THR is empty, and is associated with LSR[5]. In the FIFO
modes, this interrupt will be issued whenever the FIFO is empty.
Receive Holding Register. In the non-FIFO mode, this interrupt will be issued
when the RHR has data, or is cleared when the RHR is empty. In the FIFO mode,
this interrupt will be issued when the FIFO has reached the programmed trigger
level or is cleared when the FIFO drops below the trigger level.
logic 0 = disable the Transmit Holding Register Empty (TXRDY) interrupt
(normal default condition)
logic 1 = enable the TXRDY (ISR level 3) interrupt
logic 0 = disable the receiver ready (ISR level 2, RXRDY) interrupt (normal
default condition)
logic 1 = enable the RXRDY (ISR level 2) interrupt
Rev. 5 — 19 January 2011
…continued
SC16C850V
© NXP B.V. 2011. All rights reserved.
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