TDA8932BTW/N2,118 NXP Semiconductors, TDA8932BTW/N2,118 Datasheet - Page 36

• Manufacturer Part Number: TDA8932BTW/N2,118
• Description: IC AMP AUDIO CLASS D 32HTSSOP
• Manufacturer: NXP Semiconductors
• Type: Class Dr

Specifications of TDA8932BTW/N2,118

• Output Type: 1-Channel (Mono) or 2-Channel (Stereo)
• Package / Case: 32-TSSOP Exposed Pad, 32-eTSSOP, 32-HTSSOP
• Max Output Power X Channels @ Load: 55W x 1 @ 8 Ohm; 26.5W x 2 @ 4 Ohm
• Voltage - Supply: 10 V ~ 36 V, ±5 V ~ 18 V
• Features: Depop, Differential Inputs, Mute, Short-Circuit and Thermal Protection
• Mounting Type: Surface Mount
• Product: Class-D
• Output Power: 55 W
• Available Set Gain: 36 dB
• Common Mode Rejection Ratio (min): 75 dB
• Thd Plus Noise: 0.007 %
• Operating Supply Voltage: 22 V
• Supply Current: 0.145 mA
• Maximum Power Dissipation: 5000 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Audio Load Resistance: 8 Ohms
• Dual Supply Voltage: +/- 11 V
• Input Signal Type: Differential
• Minimum Operating Temperature: - 40 C
• Output Signal Type: Differential, Single
• Supply Type: Single or Dual
• Supply Voltage (max): 36 V
• Supply Voltage (min): 10 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935283479118

NXP Semiconductors
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UJA1079_2
Product data sheet
Fig 14. LIN transceiver timing diagram
output of receiving
output of receiving
t
A system reset will be performed if the watchdog is in Window mode and is triggered less than t
period (or in the first half of the watchdog period).
The nominal watchdog period is programmed via the NWP control bits in the WD_and_Status register (see
Window mode only.
The watchdog will be reset if it is in window mode and is triggered at least t
watchdog period (or in the second half of the watchdog period). A system reset will be performed if the watchdog is triggered more than
t
δ2 δ4
PD(RX)sym
trig(wd)2
LIN bus signal
,
after the start of the watchdog period (watchdog overflows).
=
node A
node B
V
= t
V
t
------------------------------- -
TXDL
bus rec
BAT
PD(RX)r
2 t
(
×
V
V
) max
bit
RXDL
RXDL
(
− t
PD(RX)f
)
Fig 13. Timing test circuit for LIN transceiver
.
.
t
t
PD(RX)f
bit
All information provided in this document is subject to legal disclaimers.
C
t
t
bus(dom)(max)
bus(dom)(min)
RXDL
Rev. 02 — 27 May 2010
t
PD(RX)r
t
bit
t
PD(RX)r
RXDL
TXDL
t
t
bus(rec)(min)
bus(rec)(max)
trig(wd)1
SBC
GND
BAT
t
, but not more than t
bit
DLIN
LIN
t
PD(RX)f
trig(wd)1
015aaa133
LIN core system basis chip
V
V
V
V
th(rec)RX(max)
th(dom)RX(max)
th(rec)RX(min)
th(dom)RX(min)
trig(wd)2
after the start of the watchdog
015aaa128
Table
, after the start of the
R
C
UJA1079
LIN
© NXP B.V. 2010. All rights reserved.
LIN
4); valid in watchdog
thresholds of
receiving node A
thresholds of
receiving node B
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