LM49352RLX/NOPB National Semiconductor, LM49352RLX/NOPB Datasheet - Page 29

• Manufacturer Part Number: LM49352RLX/NOPB
• Description: IC AMP AUDIO MONO D1.4W 36USMD
• Manufacturer: National Semiconductor
• Series: Boomer®, PowerWise®r
• Type: Class Dr

Specifications of LM49352RLX/NOPB

• Output Type: 1-Channel (Mono) with Mono and Stereo Headphones
• Max Output Power X Channels @ Load: 1.4W x 1 @ 8 Ohm; 65mW x 2 @ 32 Ohm
• Features: Depop, Differential Inputs, I²C, I²S, Microphone, Shutdown, Volume Control
• Mounting Type: Surface Mount
• Package / Case: 36-MicroSMDxt
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Other names: LM49352RLX

12.0 System Control
Method 1. I
12.1 I
In I
SCL and the pin SDA is used for the I
these signals need a pull-up resistor according to I
fication. The I
12.2 I
The data on SDA line must be stable during the HIGH period
of the clock signal (SCL). In other words, state of the data line
can only be changed when SCL is LOW.
12.3 I
START and STOP bits classify the beginning and the end of
the I
transitioning from HIGH to LOW while SCL line is HIGH.
STOP condition is defined as the SDA transitioning from LOW
to HIGH while SCL is HIGH. The I
START and STOP bits. The I
2
C mode the LM49352 pin SCL is used for the I
2
C session. START condition is defined as SDA signal
2
2
2
C SIGNALS
C DATA VALIDITY
C START AND STOP CONDITIONS
FIGURE 6. I
2
C Compatible Interface
2
C slave address for LM49352 is 0011010
2
C Signals: Data Validity
2
C bus is considered to be busy
2
C master always generates
2
C data signal SDA. Both
FIGURE 8. I
2
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2
C speci-
C clock
2
.
2
C Chip Address
29
after START condition and free after STOP condition. During
data transmission, I
conditions. First START and repeated START conditions are
equivalent, function-wise.
12.4 TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. Each
byte of data has to be followed by an acknowledge bit. The
acknowledge related clock pulse is generated by the master.
The transmitter releases the SDA line (HIGH) during the ac-
knowledge clock pulse. The receiver must pull down the SDA
line during the 9
receiver which has been addressed must generate an ac-
knowledge after each byte has been received.
After the START condition, the I
dress. This address is seven bits long followed by an eight bit
which is a data direction bit (R/W). The LM49352 address is
0011010
“1” indicates a READ. The second byte selects the register to
which the data will be written. The third byte contains data to
write to the selected register.
FIGURE 7. I
2
. For the eighth bit, a “0” indicates a WRITE and a
th
clock pulse, signifying an acknowledge. A
2
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C master can generate repeated START
2
C Start and Stop Conditions
2
C master sends a chip ad-
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30072724