LM49352RLX/NOPB National Semiconductor, LM49352RLX/NOPB Datasheet - Page 38

• Manufacturer Part Number: LM49352RLX/NOPB
• Description: IC AMP AUDIO MONO D1.4W 36USMD
• Manufacturer: National Semiconductor
• Series: Boomer®, PowerWise®r
• Type: Class Dr

Specifications of LM49352RLX/NOPB

• Output Type: 1-Channel (Mono) with Mono and Stereo Headphones
• Max Output Power X Channels @ Load: 1.4W x 1 @ 8 Ohm; 65mW x 2 @ 32 Ohm
• Features: Depop, Differential Inputs, I²C, I²S, Microphone, Shutdown, Volume Control
• Mounting Type: Surface Mount
• Package / Case: 36-MicroSMDxt
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Other names: LM49352RLX

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17.0 LM49352 Clock Network
(Refer to Figure 12)
The audio DAC and ADC operate at a clock frequency of 2*OSR*f
frequency of the DAC or ADC. The DAC can operate at three different OSR settings (128, 125, 64). The ADC can operate at two
different OSR settings (128, 125). For example, if the stereo DAC or ADC is set at OSR = 128, a 12.288MHz clock is required for
48kHz data. If a 12.288MHz clock is not available, then the internal PLL can be used to generate the desired clock frequency.
Otherwise, if a 12.288MHz is available, the PLL can be bypassed to reduce power consumption. The DAC clock divider or ADC
clock divider can also be used to generate the correct clock. If an 18.432 MHz clock is available, the DAC or ADC clock divider
could be set to 1.5 in order to generate a 12.288MHz clock from 18.432MHz without using a PLL.
The DAC path clock (DAC_SOURCE_CLK) and ADC path clock (ADC_SOURCE_CLK) can be driven directly by the MCLK input,
the PORT1_CLK input, the PORT2_CLK input, or PLL output.
For instances where a PLL must be used, the PLL input clock can come from three sources. The clock input to the PLL can come
from the MCLK input, the PORT1_CLK input, or the PORT2_CLK input.
The LM49352's Power Management Circuit (PMC) requires a clock that is independent from the DAC or ADC. It is recommended
to provide a
PMC clock path can be driven directly by the MCLK input, the internal 300kHz oscillator, the DAC_SOURCE_CLK, or the
ADC_SOURCE_CLK.
DAC Sample Rate
11.025
(kHz)
22.05
44.1
ADC Sample Rate
12
16
24
32
48
96
8
≈
300kHz clock at Point C. The PMC clock divider is available to generate the correct clock to the PMC block. The
11.025
(kHz)
22.05
44.1
12
16
24
32
48
8
Clock Required at A
11.2896 MHz
(OSR = 128)
2.8224 MHz
5.6448 MHz
12.288 MHz
24.576 MHz
2.048 MHz
3.072 MHz
4.096 MHz
6.144 MHz
8.192 MHz
TABLE 6. DAC Clock Requirements
TABLE 7. ADC Clock Requirements
Clock Required at B
Clock Required at A
11.2896 MHz
(OSR = 128)
2.8224 MHz
5.6448 MHz
12.288 MHz
2.75625 MHz
(OSR = 125)
2.048 MHz
3.072 MHz
4.096 MHz
6.144 MHz
8.192 MHz
5.5125 MHz
11.025 MHz
12 MHz
24 MHz
2 MHz
3 MHz
4 MHz
6 MHz
8 MHz
38
S
where OSR is the oversampling ratio and f
Clock Required at A
1.4112 MHz
2.8224 MHz
5.6448 MHz
12.288 MHz
(OSR = 64)
1.024 MHz
1.536 MHz
2.048 MHz
3.072 MHz
4.096 MHz
6.144 MHz
Clock Required at B
2.75625 MHz
(OSR = 125)
5.5125 MHz
11.025 MHz
12 MHz
2 MHz
3 MHz
4 MHz
6 MHz
8 MHz
Clock Required at A
0.7056 MHz
1.4112 MHz
2.8224 MHz
(OSR = 32)
0.512 MHz
0.768 MHz
1.024 MHz
1.536 MHz
3.072 MHz
6.144 MHz
2.048MHz
S
is the sampling