ATmega165P Atmel Corporation, ATmega165P Datasheet
ATmega165P
Specifications of ATmega165P
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ATmega165P Summary of contents
Page 1
... Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby • I/O and Packages – 54 Programmable I/O Lines – 64-lead TQFP and 64-pad QFN/MLF • Speed Grade: – ATmega165PV MHz @ 1.8V - 5.5V MHz @ 2.7V - 5.5V – ATmega165P MHz @ 2.7V - 5.5V MHz @ 4.5V - 5.5V • Temperature range: – -40°C to 85°C Industrial • Ultra-Low Power Consumption – ...
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... Pin Configurations Figure 1-1. Pinout ATmega165P DNC 1 (RXD/PCINT0) PE0 2 (TXD/PCINT1) PE1 3 (XCK/AIN0/PCINT2) PE2 4 (AIN1/PCINT3) PE3 5 (USCK/SCL/PCINT4) PE4 6 (DI/SDA/PCINT5) PE5 7 (DO/PCINT6) PE6 8 (CLKO/PCINT7) PE7 9 (SS/PCINT8) PB0 10 (SCK/PCINT9) PB1 11 (MOSI/PCINT10) PB2 12 (MISO/PCINT11) PB3 13 (OC0A/PCINT12) PB4 14 (OC1A/PCINT13) PB5 15 (OC1B/PCINT14) PB6 16 Note: 1.1 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology ...
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... Overview The ATmega165P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By execut- ing powerful instructions in a single clock cycle, the ATmega165P achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1 ...
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... Atmel ATmega165P is a powerful microcontroller that provides a highly flex- ible and cost effective solution to many embedded control applications. The ATmega165P AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. 8019K– ...
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... The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B has better driving capabilities than the other ports. Port B also serves the functions of various special features of the ATmega165P as listed on “Alternate Functions of Port B” on page 2.2.5 Port C (PC7:PC0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit) ...
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... The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega165P as listed in Chapter 2.2.8 Port F (PF7:PF0) Port F serves as the analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit) ...
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... Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 8019K–AVR–11/10 ATmega165P 7 ...
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... These code examples assume that the part specific header file is included before compilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". 8019K–AVR–11/10 ATmega165P 8 ...
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... Register File – in one clock cycle. 8019K–AVR–11/10 Block Diagram of the AVR Architecture Program Flash Counter Program Memory Instruction Register Instruction Decoder Control Lines ATmega165P Data Bus 8-bit Status and Control Interrupt Unit General Purpose SPI Registrers Unit Watchdog ...
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... The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis- ters, SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega165P has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used ...
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... The Parallel Instruction Fetches and Instruction Executions T1 clk CPU 1st Instruction Fetch 2nd Instruction Fetch 3rd Instruction Fetch 4th Instruction Fetch shows the internal timing concept for the Register File single clock ATmega165P – – SP10 SP9 SP4 ...
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... Single Cycle ALU Operation T1 clk CPU Total Execution Time Result Write Back for details. “Boot Loader Support – Read-While-Write Self-Programming” on page ATmega165P “Memory Program- “Interrupts” on page 52. The list also “Interrupts” on page 52 for more information. ...
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... Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. 8019K–AVR–11/10 ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write ; restore SREG value (I-bit) ; set Global Interrupt Enable ATmega165P 13 ...
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... Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 8019K–AVR–11/ R/W R/W R/W R ⊕ V ATmega165P R/W R/W R/W R SREG 14 ...
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... Purpose R15 Working R16 Registers R17 … R26 R27 R28 R29 R30 R31 Figure 5-4, each register is also assigned a data memory address, mapping them ATmega165P 0 Addr. 0x00 0x01 0x02 0x0D 0x0E 0x0F 0x10 0x11 0x1A X-register Low Byte 0x1B X-register High Byte ...
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... In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 8019K–AVR–11/10 The X-, Y-, and Z-registers R27 (0x1B R29 (0x1D R31 (0x1F) ATmega165P Figure 5- R26 (0x1A R28 (0x1C R30 (0x1E ...
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... For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega165P Program Counter (PC bits wide, thus addressing the 8K program memory locations. The ...
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... When using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and the 1,024 bytes of internal data SRAM in the ATmega165P are all accessible through all these addressing modes. The Register File is described in 15. ...
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... EEPROM Data Memory The ATmega165P contains 512 bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. This section describes the access between the EEPROM and the CPU, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...
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... EEPROM write function must also wait for any ongoing SPM command to finish. 8019K–AVR–11/10 “Register Description” on page 24 EEPROM Programming Time Number of Calibrated RC Oscillator Cycles 27 072 ATmega165P for supplementary description for each “Boot Loader for details about Boot Table 6-1 lists the typical pro- Typical Programming Time 3 ...
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... EECR,EEMWE ; Start eeprom write by setting EEWE sbi EECR,EEWE ret /* Wait for completion of previous write */ while(EECR & (1<<EEWE Set up address and Data Registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMWE */ EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE); ATmega165P 21 ...
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... Start eeprom read by writing EERE sbi EECR,EERE ; Read data from Data Register in r16,EEDR ret /* Wait for completion of previous write */ while(EECR & (1<<EEWE Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from Data Register */ return EEDR; ATmega165P 22 ...
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... When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega165P is a com- plex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions ...
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... General Purpose I/O Registers The ATmega165P contains three General Purpose I/O Registers. These registers can be used for storing any information, and they are particularly useful for storing global variables and Sta- tus Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are directly bit- accessible using the SBI, CBI, SBIS, and SBIC instructions ...
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... Read/Write Initial Value 8019K–AVR–11/ MSB R/W R/W R/W R MSB R/W R/W R/W R MSB R/W R/W R/W R ATmega165P LSB R/W R/W R/W R LSB R/W R/W R/W R LSB R/W R/W R/W R GPIOR2 GPIOR1 GPIOR0 ...
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... Control Unit clk ASY System Clock Prescaler Clock Multiplexer Timer/Counter External Clock Oscillator is halted, enabling USI start condition detection in all sleep modes. I/O ATmega165P Flash and CPU Core RAM EEPROM clk CPU clk FLASH Reset Logic Watchdog Timer Source clock Watchdog clock ...
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... ASY Device Clocking Options Select 1. For all fuses “1” means unprogrammed while “0” means programmed. 308. Number of Watchdog Oscillator Cycles = 5.0V) Typ Time-out ( ATmega165P (1) CKSEL3..0 1111 - 1000 0111 - 0110 0011, 0001, 0101, 0100 “Typical Charac- = 3.0V) Number of Cycles CC 4.3 ms ...
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... Start-up times for the internal calibrated RC Oscillator clock selection Start-up Time from Power- down and Power-save Reserved 1. The device is shipped with this option selected ATmega165P for more details. The device is “System Clock Prescaler” on page 33 “OSCCAL – Oscillator Calibration Register” on Table 26-2 on page 269. (1)(3) CKSEL3..0 ...
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... C1 Crystal Oscillator Operating Modes Frequency Range (MHz) (1) 0.4 - 0.9 0.9 - 3.0 3.0 - 8.0 8 This option should not be used with crystals, only with ceramic resonators. ATmega165P Figure 7-2. Either a quartz crystal or a XTAL2 (TOSC2) XTAL1 (TOSC1) GND Table 7-5. Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF) – ...
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... The Low-frequency Crystal Oscillator is optimized for use with a 32.768 kHz watch crystal. When selecting crystals, load capasitance and crystal’s Equivalent Series Resistance, ESR must be taken into consideration. Both values are specified by the crystal vendor. ATmega165P oscillator is optimized for very low power consumption, and thus when selecting crystals, see Table 7-7 Table 7-7 ...
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... Start-up Times for the Low-frequency Crystal Oscillator Clock Selection Start-up Time from Power-down and Power-save ( 32K CK 1. This option should only be used if frequency stability at start-up is not important for the application. ATmega165P XTAL2 (TOSC2) XTAL1 (TOSC1) Typ. (pF) Max. (pF) 6.5 = 5.0V) Recommended Usage CC ...
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... Crystal Oscillator Clock Frequency Frequency Range MHz Start-up Times for the External Clock Selection Start-up Time from Power- Additional Delay from down and Power-save Reset ( ATmega165P XTAL2 XTAL1 GND = 5.0V) Recommended Usage CC 14CK BOD enabled 14CK + 4.1 ms Fast rising power ...
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... Oscillator. See crystal requirements. ATmega165P share the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) with XTAL1 and XTAL2. When using the Timer/Counter Oscillator, the system clock needs to be four times the oscillator frequency. Due to this and the pin sharing, the Timer/Counter Oscillator can only be used when the Calibrated Internal RC Oscillator is selected as system clock source ...
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... R/W Device Specific Calibration Value Table 26-2 on page 301. The application software can write this register to change 301. Calibration outside that range is not guaranteed CLKPCE – – R 35. ATmega165P CAL3 CAL2 CAL1 R/W R/W R – CLKPS3 CLKPS2 CLKPS1 ...
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... ATmega165P CLKPS0 Clock Division Factor 128 0 256 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 35 ...
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... SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from sleep reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. 8019K–AVR–11/10 presents the different clock systems in the ATmega165P, and their distri- Oscillators (2) X ...
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... The wake-up period is defined by the same CKSEL Fuses that define the Reset Time-out period, as described in 8019K–AVR–11/10 and clk , while allowing the other clocks to run. CPU FLASH , clk , and clk I/O CPU “Clock Sources” on page ATmega165P , while allowing the other clocks to run. FLASH “External Interrupts” on page 57 27. 37 ...
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... Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption. See sleep modes, the clock is already stopped. 8019K–AVR–11/10 “PRR – Power Reduction Register” on page “Supply Current of I/O modules” on page 313 ATmega165P 41, pro- for examples. In all other 38 ...
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... Analog Comparator” on page 200 for details on the start-up time. “Watchdog Timer” on page 47 for details on how to configure the Watchdog Timer. ATmega165P “ADC - Analog to Digital Converter” on page for details on how to configure the Ana- “Brown-out Detection” on page 46 “Internal Volt- ...
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... Input Enable and Sleep Modes” on page 65 /2, the input buffer will use excessive power input pin can cause significant current even in active mode. Digital CC “DIDR1 – Digital Input Disable Register 1” on page 203 for details. ATmega165P for details on and “DIDR0 – Digital 40 ...
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... Standby mode is only recommended for use with external crystals or resonators – – – ATmega165P – SM2 SM1 SM0 R R/W R/W R Table Sleep Mode Idle ADC Noise Reduction Power-down Power-save Reserved ...
Page 42
... Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot use the ADC input MUX when the ADC is shut down. Note: 8019K–AVR–11/10 The Analog Comparator is disabled using the ACD-bit in the and Status Register” on page 202. ATmega165P “ACSR – Analog Comparator Control 42 ...
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... Reset Sources The ATmega165P has five sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. • ...
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... Watchdog Oscillator Clock Generator CKSEL[3:0] SUT[1:0] “System and Reset Characteristics” on page rise. The RESET signal is activated again, without any delay, CC decreases below the detection level. CC ATmega165P DATA BUS MCU Status Register (MCUSR) Delay Counters CK TIMEOUT 302. The POR is activated whenever 44 ...
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... CC V RST RESET t TOUT RESET MCU Start-up, RESET Extended Externally V POT V CC RESET RESET “System and Reset Characteristics” on page External Reset During Operation CC ATmega165P CC V RST t TOUT 302) will generate a – on its positive edge, the RST – has expired. TOUT 45 ...
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... Brown-out Detection ATmega165P has an On-chip Brown-out Detection (BOD) circuit for monitoring the V during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as V ...
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... Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATmega165P resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to ...
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... WDE must be written to one to start the timed sequence. Within the next four clock cycles, in the same operation, write the WDP bits as desired, but with the WDCE bit cleared. The value written to the WDE bit is irrelevant. 8019K–AVR–11/10 Watchdog Timer WATCHDOG OSCILLATOR ATmega165P 48 ...
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... WDTCR, r16 ; Turn off WDT ldi r16, (0<<WDE) out WDTCR, r16 ret (1) /* Reset WDT */ __watchdog_reset(); /* Write logical one to WDCE and WDE */ WDTCR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCR = 0x00; 1. See “About Code Examples” on page ATmega165P 8. 49 ...
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... JTRF R – – – WDCE R See “Timed Sequences for Changing the Configuration of the ATmega165P WDRF BORF EXTRF PORF R/W R/W R/W R/W See Bit Description WDE WDP2 WDP1 WDP0 R/W R/W R/W R ...
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... Also see Figure 27-54 on page 336. ATmega165P Typical Time-out at Typical Time-out 3. 5. 15.4 ms 14.7 ms 30.8 ms 29.3 ms 61.6 ms 58.7 ms 0.12 s 0.12 s 0.25 s 0.23 s 0.49 s 0.47 s 1.0 s 0.9 s 2.0 s 1.9 s ...
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... Interrupts This section describes the specifics of the interrupt handling as performed in ATmega165P. For a general explanation of the AVR interrupt handling, refer to page 12. 10.1 Interrupt Vectors in ATmega165P Table 10-1. Vector No Notes: Table 10-2 on page 53 tions of BOOTRST and IVSEL settings. ...
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... This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 10-2. BOOTRST Note: The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega165P is: Address Labels Code 0x0000 0x0002 0x0004 0x0006 ...
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... PCINT0 ... ... jmp SPM_RDY RESET: ldi r16,high(RAMEND); Main program start out SPH,r16 ldi r16,low(RAMEND) ATmega165P Comments ; Set Stack Pointer to top of RAM ; Enable interrupts ; IRQ0 Handler ; PCINT0 Handler ; ; Store Program Memory Ready Handler ; IRQ0 Handler ; PCINT0 Handler ; ; Store Program Memory Ready Handler ...
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... Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section Write Self-Programming” on page 250 ATmega165P ; Enable interrupts 56. “Boot Loader Support – Read-While- for details on Boot Lock bits ...
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... MCUCR; MCUCR = temp | (1<<IVCE); */ MCUCR = temp | (1<<IVSEL JTD - - R for details. 55. See Code Example. ATmega165P PUD – – IVSEL R R “Boot Loader Support – Read-While-Write “Moving Interrupts Between Application and Boot ...
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... An example of timing of a pin change interrupt is shown in Figure 11-1. Pin Change Interrupt 8019K–AVR–11/10 “Clock Systems and their Distribution” on page pin_lat PCINT( pin_sync LE clk PCINT(0) in PCMSK(x) clk PCINT(n) pin_lat pin_sync pcint_in_(n) pcint_syn pcint_setflag PCIF ATmega165P 26. Figure 11-1. pcint_in_(0) 0 pcint_syn pcint_setflag x clk 26. Low PCIF 57 ...
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... Any logical change on INT0 generates an interrupt request 0 The falling edge of INT0 generates an interrupt request 1 The rising edge of INT0 generates an interrupt request PCIE1 PCIE0 – – R/W R ATmega165P – – ISC01 ISC00 R R R/W R – ...
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... I/O pin is disabled. 8019K–AVR–11/ PCIF1 PCIF0 – – R/W R PCINT15 PCINT14 PCINT13 PCINT12 R/W R/W R/W R ATmega165P – – – INTF0 R PCINT11 PCINT10 PCINT9 PCINT8 R/W R/W R/W R EIFR ...
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... If PCINT7:0 is set and the PCIE0 bit in EIMSK is set, pin change interrupt is enabled on the cor- responding I/O pin. If PCINT7:0 is cleared, pin change interrupt on the corresponding I/O pin is disabled. 8019K–AVR–11/ PCINT7 PCINT6 PCINT5 PCINT4 R/W R/W R/W R ATmega165P PCINT3 PCINT2 PCINT1 PCINT0 R/W R/W R/W R PCMSK0 60 ...
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... Ground as indicated in CC for a complete list of parameters. Pxn C pin “Register Description” on page 67. Refer to the individual module sections for a full description of the alter- ATmega165P Figure 12-1. Refer to “Electrical Char Logic See Figure "General Digital I/O" for Details 79. “ ...
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... I/O CLOCK I/O 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. 79, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits ATmega165P Figure 12-2 PUD Q D DDxn Q ...
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... Input 1 1 Input 0 X Output 1 X Output Figure 12-2 on page shows a timing diagram of the synchronization when reading an externally applied pin ATmega165P Pull-up Comment No Tri-state (Hi-Z) Yes Pxn will source current if ext. pulled low. No Tri-state (Hi-Z) No Output Low (Sink) No Output High (Source) 62, the PINxn Register bit and the preced- ...
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... SYSTEM CLK XXX SYNC LATCH PINxn r17 Figure 12-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of r16 out PORTx, r16 PINxn r17 ATmega165P XXX in r17, PINx 0x00 t pd, max t pd, min 0xFF nop in r17, PINx 0x00 ...
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... Figure 12-2 on page 62, the digital input signal can be clamped to ground at the “Alternate Port Functions” on page ATmega165P /2. CC 67. 65 ...
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... In this case, the pull-up will be disabled during reset. If low power consumption during reset is important recommended to use an external pull-up or pull-down. Connecting unused pins directly to V accidentally configured as an output. 8019K–AVR–11/10 or GND is not recommended, since this may cause excessive currents if the pin is CC ATmega165P 66 ...
Page 67
... WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. All other signals are unique for each pin. summarizes the function of the overriding signals. The pin and port Figure 12-5 are not shown in the succeeding tables. The overriding signals are ATmega165P Figure 12-2 on page 62 PUD Q D ...
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... Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer. This is the Analog Input/output to/from alternate functions. The Analog signal is connected directly to the pad, and can be used bi- Input/Output directionally. ATmega165P 68 ...
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... OC0A/PCINT12 (Output Compare and PWM Output A for Timer/Counter0 or Pin Change Interrupt12). MISO/PCINT11 (SPI Bus Master Input/Slave Output or Pin Change Interrupt11). MOSI/PCINT10 (SPI Bus Master Output/Slave Input or Pin Change Interrupt10). SCK/PCINT9 (SPI Bus Serial Clock or Pin Change Interrupt9). SS/PCINT8 (SPI Slave Select input or Pin Change Interrupt8). ATmega165P Table 12-3. 69 ...
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... PUT constitute the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. 8019K–AVR–11/10 and Table 12-5 on page 71 relate the alternate functions of Port B to the Figure 12-5 on page 67. SPI MSTR INPUT and SPI SLAVE OUT- ATmega165P 70 ...
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... SPE • MSTR SPI SLAVE OUTPUT SPI MSTR OUTPUT – – PCINT11 • PCIE1 PCINT10 • PCIE1 1 1 PCINT11 INPUT PCINT10 INPUT SPI MSTR INPUT SPI SLAVE INPUT – – ATmega165P PB5/OC1A/ PB4/OC0A/ PCINT13 PCINT12 OC1A ENABLE OC0A ENABLE ...
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... Port D to the overriding signals shown in 67. Overriding Signals for Alternate Functions in PD1..PD0 PD1/INT0 – INT0 ENABLE INT0 ENABLE INT0 INPUT – ATmega165P Table 12-6. PD0/ICP1 – ICP1 INPUT – ...
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... USCK/SCL/PCINT4 (USART External Clock Input/Output or TWI Serial Clock or Pin Change Interrupt4) AIN1/PCINT3 (Analog Comparator Negative Input or Pin Change Interrupt3) XCK/AIN0/ PCINT2 (USART External Clock or Analog Comparator Positive Input or Pin Change Interrupt2) TXD/PCINT1 (USART Transmit Pin or Pin Change Interrupt1) RXD/PCINT0 (USART Receive Pin or Pin Change Interrupt0) ATmega165P Table 12-8. 73 ...
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... DO I/O – – PCINT7 • PCIE0 PCINT6 • PCIE0 1 1 PCINT7 INPUT PCINT6 INPUT – – 1. CKOUT is one if the CKOUT Fuse is programmed. ATmega165P PE5/DI/SDA/ PE4/USCK/SCL/ PCINT5 PCINT4 USI_TWO-WIRE USI_TWO-WIRE 0 0 USI_TWO-WIRE USI_TWO-WIRE (SDA + PORTE5) • (USI_SCL_HOLD • DDE5 PORTE4) + DDE4 USI_TWO-WIRE • ...
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... ADC6/TDO (ADC input channel 6 or JTAG Test Data Output) ADC5/TMS (ADC input channel 5 or JTAG Test mode Select) ADC4/TCK (ADC input channel 4 or JTAG Test ClocK) ADC3 (ADC input channel 3) ADC2 (ADC input channel 2) ADC1 (ADC input channel 1) ADC0 (ADC input channel 0) ATmega165P PE1/TXD/ PCINT1 TXENn 0 TXENn 1 ...
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... PF6/ADC6/TDO JTAGEN JTAGEN 1 1 JTAGEN JTAGEN 0 SHIFT_IR + SHIFT_DR 0 JTAGEN 0 TDO – – JTAGEN JTAGEN 0 0 – – TDI ADC6 INPUT ADC7 INPUT ATmega165P PF5/ADC5/TMS PF4/ADC4/TCK JTAGEN JTAGEN 1 1 JTAGEN JTAGEN – – JTAGEN JTAGEN 0 1 – – TMS ...
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... ADC3 INPUT ADC2 INPUT Alternate Function RESET T0 (Timer/Counter0 Clock Input) T1 (Timer/Counter1 Clock Input) – – – 1. Port G, PG5 is input only. Pull-up is always on. See fuse. ATmega165P PF1/ADC1 PF0/ADC0 – – ...
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... PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 8019K–AVR–11/10 and Table 12-15 relates the alternate functions of Port G to the overrid- Figure 12-5 on page 67. PG4/ – INPUT – ATmega165P PG3/ – INPUT – 78 ...
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... PORTB4 R/W R/W R/W R DDB7 DDB6 DDB5 DDB4 R/W R/W R/W R PINB7 PINB6 PINB5 PINB4 R/W R/W R/W R/W N/A N/A N/A N/A ATmega165P – – IVSEL IVCE R R R/W R PORTA3 PORTA2 PORTA1 PORTA0 R/W R/W R/W R DDA3 DDA2 DDA1 DDA0 ...
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... PIND5 PIND4 R/W R/W R/W R/W N/A N/A N/A N PORTE7 PORTE6 PORTE5 PORTE4 R/W R/W R/W R DDE7 DDE6 DDE5 DDE4 R/W R/W R/W R ATmega165P PORTC3 PORTC2 PORTC1 PORTC0 R/W R/W R/W R DDC3 DDC2 DDC1 DDC0 R/W R/W R/W R PINC3 PINC2 PINC1 PINC0 R/W ...
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... – – DDG5 DDG4 R – – PING5 PING4 R N/A ATmega165P PINE3 PINE2 PINE1 PINE0 R/W R/W R/W R/W N/A N/A N/A N PORTF3 PORTF2 PORTF1 PORTF0 R/W R/W R/W R DDF3 DDF2 DDF1 ...
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... T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clk 8019K–AVR–11/10 “Pinout ATmega165P” on page “Register Description” on page 93. TCCRn ...
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... OCR0A Register. The assignment is dependent on the mode of operation. “Timer/Counter0 and Timer/Counter1 Prescalers” on page DATA BUS count clear TCNTn Control Logic direction bottom ATmega165P See “Output 126. TOVn (Int.Req.) Clock Select Edge Detector clk Tn ( From Prescaler ) ...
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... Signalize that TCNT0 has reached minimum value (zero). ). clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear or T0 87. See “Modes of Operation” on page 87. shows a block diagram of the Output Compare unit. ATmega165P in the following ...
Page 85
... This feature allows OCR0A to be initial- ized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is enabled. 8019K–AVR–11/10 DATA BUS OCRnx = (8-bit Comparator ) Waveform Generator WGMn1:0 ATmega165P TCNTn OCFnx (Int.Req.) OCnx COMnx1:0 85 ...
Page 86
... Register bit for the OC0A pin (DDR_OC0A) must be set as output before the OC0A value is vis- ible on the pin. The port override function is independent of the Waveform Generation mode. 8019K–AVR–11/10 COMnx1 Waveform COMnx0 D Generator FOCn OCnx D PORT D DDR clk I/O ATmega165P Figure 13 OCn Pin shows a sim- 86 ...
Page 87
... See “Register Description” on page 93. Table 13-3 on page 94, and for phase correct PWM refer to See “Compare Match Output Unit” on page 86. Figure 13-8 on page and Figure 13-11 on page 92 ATmega165P 94. For fast PWM mode, refer to Table 13-5 on page 94. 91, Figure 13-9 on page in “Timer/Counter Timing Diagrams” on page ...
Page 88
... DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. 8019K–AVR–11/10 Figure clk_I/O = ------------------------------------------------- - f ⋅ ⋅ ( OCnx OCRnx ATmega165P 13-5. The counter value (TCNT0) OCnx Interrupt Flag Set (COMnx1 OC0 ) 88 = ...
Page 89
... COM0A1:0 bits). 8019K–AVR–11/10 Figure 13-6. The TCNT0 value is in the timing diagram shown as a his OCnxPWM ATmega165P OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set (COMnx1 (COMnx1 Table 13-4 on page 94). The actual ...
Page 90
... Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. 8019K–AVR–11/ when OCR0A is set to zero. This OC0 clk_I ATmega165P Figure 13-7. OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set (COMnx1 (COMnx1 ...
Page 91
... TCNTn TOVn 8019K–AVR–11/10 f OCnxPCPWM Figure 13-7 on page 90 Figure 13-8 contains timing data for basic Timer/Counter operation. The figure I/O Tn /1) I/O MAX - 1 ATmega165P Table 13-5 on page f clk_I/O = ----------------- - ⋅ N 510 OCn has a transition from high to low Figure 13-7 on page 90. When the OCR0A value ) is therefore shown ...
Page 92
... OCF0A in all modes except CTC mode. I/O Tn /8) I/O OCRnx - 1 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode. caler (f /8) clk_I/O I/O Tn /8) I/O TOP - 1 ATmega165P /8) clk_I/O MAX BOTTOM OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP BOTTOM + 1 /8) clk_I/O OCRnx + 2 ...
Page 93
... PWM, Phase Correct 1 0 CTC 1 1 Fast PWM 1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. ATmega165P COM0A0 WGM01 CS02 CS01 R/W ...
Page 94
... A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the com- pare match is ignored, but the set or clear is done at TOP. See page 90 for more details. ATmega165P (1) “Fast PWM Mode” on (1) “Phase Correct PWM Mode” on ...
Page 95
... I External clock source on T0 pin. Clock on falling edge External clock source on T0 pin. Clock on rising edge R/W R/W R/W R R/W R/W R/W R ATmega165P TCNT0[7:0] R/W R/W R OCR0A[7:0] R/W R/W R TCNT0 R OCR0A ...
Page 96
... – – – – ATmega165P – – OCIE0A TOIE0 R R R/W R – – OCF0A TOV0 R R R/W R ...
Page 97
... Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the The PRTIM1 bit in enable Timer/Counter1 module. 8019K–AVR–11/10 “Pinout ATmega165P” on page “Register Description” on page “PRR – Power Reduction Register” on page 41 ATmega165P Figure 14-1 on page 98 ...
Page 98
... PWM or variable frequency output on the Output Compare pin (OC1A/B). 8019K–AVR–11/10 Count Clear Control Logic Direction Timer/Counter TCNTn = OCRnA = OCRnB ICRn TCCRnA 1. Refer to Figure 1-1 on page 2 and pin placement and description. ATmega165P (1) TOVn (Int.Req.) Clock Select clk Tn Edge Detector TOP BOTTOM ( From Prescaler ) = = 0 OCnA (Int.Req.) Waveform ...
Page 99
... The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF the value stored in the OCR1A or ICR1 Register. The assignment is dependent of the mode of operation. ATmega165P See “AC 99 ...
Page 100
... Therefore, when both 8019K–AVR–11/10 (1) ... ; Set TCNT1 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ... (1) unsigned int i; ... /* Set TCNT1 to 0x01FF */ TCNT1 = 0x1FF; /* Read TCNT1 into TCNT1; ... 1. See “About Code Examples” on page 8. ATmega165P 100 ...
Page 101
... Restore global interrupt flag out SREG,r18 ret (1) unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ __disable_interrupt(); /* Read TCNT1 into TCNT1; /* Restore global interrupt flag */ SREG = sreg; return i; 1. See “About Code Examples” on page 8. ATmega165P 101 ...
Page 102
... SREG,r18 ret (1) unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ __disable_interrupt(); /* Set TCNT1 TCNT1 = i; /* Restore global interrupt flag */ SREG = sreg; 1. See “About Code Examples” on page 8. “Timer/Counter0 and Timer/Counter1 Prescalers” on page ATmega165P 126. 102 ...
Page 103
... Signalize that TCNT1 has reached minimum value (zero). ). The clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear “Modes of Operation” on page ATmega165P TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ( From Prescaler ) TOP BOTTOM 109 ...
Page 104
... TEMP Register. 8019K–AVR–11/10 DATA BUS TEMP (8-bit) ICRnH (8-bit) ICRnL (8-bit) ICRn (16-bit Register) WRITE ACO* ACIC* Analog Comparator ATmega165P Figure 14-3. The elements of (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC ICES Noise Edge Canceler Detector ICFn (Int ...
Page 105
... Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICR1 8019K–AVR–11/10 100. ATmega165P “Accessing 16-bit Registers” (Figure 15-1 on page 126). The edge detector is also ...
Page 106
... Output Compare unit. The small “n” in the register and DATA BUS TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) OCRnxL (8-bit) OCRnx (16-bit Register) TOP BOTTOM ATmega165P (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) = (16-bit Comparator ) OCFnx (Int.Req.) Waveform Generator WGMn3:0 COMnx1:0 ...
Page 107
... Normal mode. The OC1x Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM1x[1:0] bits are not double buffered together with the compare value. Changing the COM1x[1:0] bits will take effect immediately. 8019K–AVR–11/10 100. ATmega165P “Accessing 16-bit Registers” 107 ...
Page 108
... Note that some COM1x1:0 bit settings are reserved for certain modes of operation. The COM1x[1:0] bits have no effect on the Input Capture unit. 8019K–AVR–11/10 Waveform Generator I/O for details. See “Register Description” on page 119. ATmega165P Figure 14 OCnx ...
Page 109
... Table 14-1 on page 119, and for phase correct and phase and frequency correct PWM refer to 120. See “Compare Match Output Unit” on page 108. “Timer/Counter Timing Diagrams” on page ATmega165P 119. For fast PWM mode refer to 117. 109 ...
Page 110
... OCR1A is set to zero (0x0000). The waveform frequency clk_I -------------------------------------------------- - ⋅ OCnA 2 N ATmega165P Figure 14-6. The counter value (TCNT1) OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnA1 clk_I/O ⋅ OCRnA 110 ...
Page 111
... OC1A or ICF1 Flag is set at the same timer clock cycle as TOV1 is set when either OCR1A 8019K–AVR–11/10 log R = ---------------------------------- - FPWM ATmega165P ( ) TOP + log OCRnx/TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set ...
Page 112
... OC1A toggle in CTC mode, except the double buffer feature of the Output Com- pare unit is enabled in the fast PWM mode. 8019K–AVR–11/10 f clk_I ---------------------------------- - ⋅ ( OCnxPWM TOP = f /2 when OCR1A is set to zero (0x0000). This feature clk_I/O 1 ATmega165P Table on page 119). The actual ) 112 ...
Page 113
... Figure 14-8. Phase Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period 8019K–AVR–11/ log 1 TOP + R = ---------------------------------- - PCPWM log ATmega165P Figure 14-8. The figure OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom) (COMnx1 (COMnx1 113 ...
Page 114
... PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A is used to define the TOP value (WGM1[3:0] = 11) and COM1A[1: the OC1A out- put will toggle with a 50% duty cycle. 8019K–AVR–11/10 Figure 14-8 on page 113 f clk_I --------------------------- - ⋅ ⋅ OCnxPCPWM 2 N TOP ATmega165P illustrates, Table 14-3 on page 120). 114 ...
Page 115
... PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a compare match occurs. 8019K–AVR–11/10 and Figure 14-9 on page 116 PFCPWM Figure 14-9 on page ATmega165P ( ) log 1 TOP + ---------------------------------- - log 116. The figure shows phase and fre- ...
Page 116
... The actual OC1x value will only be visible on the port pin if the data direction for f OCnxPFCPWM ATmega165P OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Updateand TOVn Interrupt Flag Set ...
Page 117
... I/O clk Tn (clk /1) I/O TCNTn OCRnx - 1 OCRnx OCFnx shows the same timing data, but with the prescaler enabled. clk I/O clk Tn (clk /8) I/O TCNTn OCRnx - 1 OCRnx OCFnx ATmega165P ) is therefore shown OCRnx OCRnx + 1 OCRnx Value OCRnx OCRnx + 1 OCRnx Value OCRnx + 2 /8) clk_I/O OCRnx + 2 117 ...
Page 118
... I/O TCNTn TOP - 1 (CTC and FPWM) TCNTn TOP - 1 (PC and PFC PWM) TOVn (FPWM) (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) ATmega165P TOP BOTTOM BOTTOM + 1 TOP TOP - 1 TOP - 2 New OCRnx Value /8) clk_I/O TOP BOTTOM BOTTOM + 1 TOP TOP - 1 TOP - 2 New OCRnx Value ...
Page 119
... A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In this case the compare match is ignored, but the set or clear is done at BOTTOM PWM Mode” on page 111. for more details. ATmega165P COM1B0 – – WGM11 R/W ...
Page 120
... A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. “Phase Correct PWM Mode” on page 113. Table 14-4 on page ATmega165P Description Normal port operation, OC1A/OC1B disconnected. WGM1[3: 11: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected ...
Page 121
... CTC 0 1 (Reserved Fast PWM 1 1 Fast PWM ICNC1 ICES1 – WGM13 R/W R ATmega165P Update of x TOP OCR1 0xFFFF Immediate 0x00FF TOP 0x01FF TOP 0x03FF TOP OCR1A Immediate 0x00FF BOTTOM 0x01FF BOTTOM 0x03FF BOTTOM ICR1 BOTTOM OCR1A BOTTOM ...
Page 122
... External clock source on T1 pin. Clock on falling edge External clock source on T1 pin. Clock on rising edge FOC1A FOC1B – – R/W R ATmega165P 117 – – – Figure 0 – TCCR1C R 0 122 ...
Page 123
... TCNT1[15:8] TCNT1[7:0] R/W R/W R/W R OCR1A[15:8] OCR1A[7:0] R/W R/W R/W R OCR1B[15:8] OCR1B[7:0] R/W R/W R/W R See “Accessing 16-bit Registers” on page 100. ATmega165P R/W R/W R/W R See “Accessing 16-bit R/W R/W R/W R R/W R/W R/W R TCNT1H TCNT1L ...
Page 124
... ICIE1 “Interrupts” on page 52) is executed when the ICF1 Flag, located in TIFR1, is set. “Interrupts” on page “Interrupts” on page 52) is executed when the TOV1 Flag, located in TIFR1, is set. ATmega165P ICR1[15:8] ICR1[7:0] R/W R/W R – ...
Page 125
... TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. 8019K–AVR–11/ – – ICF1 – R ATmega165P – OCF1B OCF1A TOV1 R R/W R/W R Table 14-4 on page 121 for the TOV1 ...
Page 126
... Alternatively, one of four taps from the prescaler can be used CLK_I/O /1024. CLK_I/O ). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization T0 /clk Synchronization ATmega165P CLK_I/O pulse for each positive (CSn[2: negative Edge Detector /8, f /64, CLK_I/O Figure 15-1 ). The latch clk ...
Page 127
... Figure 15-2. Prescaler for Timer/Counter0 and Timer/Counter1 clk I/O PSR10 T0 T1 Note: 8019K–AVR–11/10 < f /2) given a 50/50% duty cycle. Since the edge detector uses ExtClk clk_I/O Clear Synchronization Synchronization clk 1. The synchronization logic on the input pins ( ATmega165P (1) T1 T1/T0) is shown in Figure 15-1 on page /2.5. clk_I/O clk T0 126. 127 ...
Page 128
... TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. 8019K–AVR–11/ TSM – – – R ATmega165P – – PSR2 PSR10 GTCCR R R R/W R 128 ...
Page 129
... Timer/Counter is shown in of I/O pins, refer to I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the Figure 16-1. 8-bit Timer/Counter Block Diagram 8019K–AVR–11/10 “Pinout ATmega165P” on page “Register Description” on page TCCRnx count clear Control Logic ...
Page 130
... OCR2A Register. The assignment is dependent on the mode of operation default equal to the MCU clock, clk T2 146. For details on clock sources and prescaler, see 142. shows a block diagram of the counter and its surrounding environment. ATmega165P See“Output . When the AS2 I/O “ASSR Figure 130 ...
Page 131
... Signalizes that TCNT2 has reached minimum value (zero). ). clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear or T2 134. 134). shows a block diagram of the Output Compare unit. ATmega165P TOVn (Int.Req.) T/C clk Tn Oscillator Prescaler top TOSC1 ...
Page 132
... OCR2A value, the compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is downcounting. 8019K–AVR–11/10 DATA BUS OCRnx = (8-bit Comparator ) top bottom Waveform Generator FOCn WGMn1:0 ATmega165P TCNTn OCFnx (Int.Req.) OCnx COMnx1:0 132 ...
Page 133
... The design of the Output Compare pin logic allows initialization of the OC2A state before the output is enabled. Note that some COM2A[1:0] bit settings are reserved for certain modes of operation. 8019K–AVR–11/10 Waveform Generator clk I/O See “Register Description” on page 143. ATmega165P Figure 16 OCnx ...
Page 134
... Table 16-3 on page 144, and for phase correct PWM refer to See “Compare Match Output Unit” on page 133. “Timer/Counter Timing Diagrams” on page Figure 16-5 on page ATmega165P 144. For fast PWM mode, refer to Table 16-5 on page 144. 138. 135. The counter value ...
Page 135
... The counter is then cleared at the following timer clock cycle. The timing diagram for the fast 8019K–AVR–11/ clk_I ------------------------------------------------- - ⋅ ⋅ ( OCnx OCRnx Flag is set in the same timer clock cycle that the TOV2 ATmega165P OCnx Interrupt Flag Set (COMnx1 OC2A ) 135 = ...
Page 136
... Compare unit is enabled in the fast PWM mode. 8019K–AVR–11/10 Figure 16-6. The TCNT2 value is in the timing diagram shown as a his OCnxPWM = f oc2 ATmega165P OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set (COMnx1 (COMnx1 Table 16-4 on page f clk_I/O ----------------- - ⋅ N 256 /2 when OCR2A is set to zero ...
Page 137
... PWM output can be generated by setting the COM2A[1:0] to three (see 144). The actual OC2A value will only be visible on the port pin if the data direction for the port 8019K–AVR–11/ ATmega165P Figure 16-7. OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set ...
Page 138
... Timer/Counter operation. The figure shows the clk I/O clk Tn (clk /1) I/O TCNTn MAX - 1 TOVn shows the same timing data, but with the prescaler enabled. ATmega165P f clk_I/O = ----------------- - ⋅ N 510 OCn has a transition from high to low Figure 16-7 on page 137. When the OCR2A value should be replaced by I/O ...
Page 139
... TCNTn OCRnx - 1 OCRnx OCFnx shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. caler (f /8) clk_I/O clk I/O clk Tn (clk /8) I/O TCNTn TOP - 1 (CTC) OCRnx OCFnx ATmega165P /8) clk_I/O MAX BOTTOM BOTTOM + 1 OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM BOTTOM + 1 TOP /8) clk_I/O OCRnx + 2 139 ...
Page 140
... The user is advised to wait for at least one second before using Timer/Counter2 after power-up or wake-up from Power-down or Standby mode. The contents of all Timer/Counter2 Registers must be considered lost after a wake-up 8019K–AVR–11/10 Enable interrupts, if needed. ATmega165P 140 ...
Page 141
... Interrupt Flag. The Output Compare pin is changed on the timer clock and is not synchronized to the processor clock. 8019K–AVR–11/10 ) again becomes active, TCNT2 will read as the previous value (before entering sleep) ATmega165P 141 ...
Page 142
... T2S Clear TIMER/COUNTER2 CLOCK SOURCE . By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously IO /256, and clk /1024. Additionally, clk T2S T2S ATmega165P 10-BIT T/C PRESCALER 0 clk T2 . clk is by default connected to the main T2S T2S /8, clk /32, clk T2S T2S as well as 0 (stop) may be selected ...
Page 143
... PWM, Phase Correct 1 0 CTC 1 1 Fast PWM 1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM2[1:0] definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. ATmega165P COM2A0 WGM21 CS22 CS21 R/W ...
Page 144
... A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the com- pare match is ignored, but the set or clear is done at TOP. See page 137 for more details. ATmega165P (1) “Fast PWM Mode” on page 135 (1) “Phase Correct PWM Mode” on ...
Page 145
... clk TCNT2[7:0] R/W R/W R/W R OCR2A[7:0] R/W R/W R/W R ATmega165P /(No prescaling) /8 (From prescaler) /32 (From prescaler) /64 (From prescaler) /128 (From prescaler) /256 (From prescaler) /1024 (From prescaler R/W R/W R/W R R/W R/W R/W R Table TCNT2 ...
Page 146
... – – – EXCLK AS2 R/W R ATmega165P – – OCIE2A TOIE2 R R R/W R – – OCF2A TOV2 R R R/W R ...
Page 147
... TSM bit is set. Refer to the description of the chronization Mode” on page 128 8019K–AVR–11/ TSM – – – R for a description of the Timer/Counter Synchronization mode. ATmega165P . When AS2 is I – – PSR2 PSR10 GTCCR R R R/W R “ ...
Page 148
... Wake-up from Idle Mode • Double Speed (CK/2) Master SPI Mode 17.2 Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega165P and peripheral devices or between several AVR devices. The PRSPI bit in enable SPI module. Figure 17-1. SPI Block Diagram /2/4/8/16/32/64/128 Note: 8019K– ...
Page 149
... In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the minimum low and high periods should be: Low period: High period: longer than 2 CPU clock cycles. 8019K–AVR–11/10 longer than 2 CPU clock cycles. ATmega165P Figure 17-2. The sys- SHIFT ENABLE 149 ...
Page 150
... SPI Pin Overrides Direction, Master SPI User Defined Input User Defined User Defined 1. See “Alternate Functions of Port B” on page 69 direction of the user defined SPI pins. ATmega165P “Alternate Port Direction, Slave SPI Input User Defined Input Input for a detailed description of how to define the 150 ...
Page 151
... Set MOSI and SCK output, all others input */ DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); /* Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) ; 1. “About Code Examples” on page ATmega165P 8. 151 ...
Page 152
... SPI_SlaveReceive ; Read received data and return in r16,SPDR ret (1) /* Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); /* Wait for reception complete */ while(!(SPSR & (1<<SPIF))) ; /* Return Data Register */ return SPDR; 1. “About Code Examples” on page ATmega165P 8. 152 ...
Page 153
... Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possi- bility that SS is driven low, the interrupt should always check that the MSTR bit is still set. If the MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI Master mode. 8019K–AVR–11/10 ATmega165P 153 ...
Page 154
... SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB Bit 6 LSB first (DORD = 1) LSB Bit 1 ATmega165P 155, as done below: Trailing eDge Setup (Falling) Sample (Falling) Setup (Rising) Sample (Rising) Bit 4 Bit 3 Bit 2 Bit 1 LSB Bit 3 Bit 4 Bit 5 ...
Page 155
... Figure 17-3 on page 154 and CPOL Functionality CPOL Leading Edge 0 Rising 1 Falling Figure 17-3 on page 154 CPHA Functionality CPHA Leading Edge 0 Sample 1 Setup ATmega165P CPOL CPHA SPR1 SPR0 R/W R/W R/W R Figure 17-4 on page 154 for an example. The Trailing Edge Falling ...
Page 156
... Master mode (see clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work lower. The SPI interface on the ATmega165P is also used for program memory and EEPROM down- loading or uploading. See 8019K–AVR–11/10 Relationship Between SCK and the Oscillator Frequency ...
Page 157
... The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis- ter causes the Shift Register Receive buffer to be read. 8019K–AVR–11/ MSB R/W R/W R/W R ATmega165P LSB R/W R/W R/W R SPDR Undefined 157 ...
Page 158
... Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete • Multi-processor Communication Mode • Double Speed Asynchronous Communication Mode The PRUSART0 bit in enable USART0 module. 8019K–AVR–11/10 “PRR – Power Reduction Register” on page 41 ATmega165P must be written to zero to 158 ...
Page 159
... CPU accessible I/O Registers and I/O pins are shown in bold. (1) UBRR[H:L] BAUD RATE GENERATOR UDR (Transmit) TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER UDR (Receive) UCSRA 1. Refer to Figure 1-1 on page 2 and placement. ATmega165P Clock Generator OSC SYNC LOGIC PIN CONTROL Transmitter TX CONTROL PARITY GENERATOR PIN CONTROL ...
Page 160
... XCK pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCK pin is only active when using synchronous mode. Figure 18-2 on page 161 8019K–AVR–11/10 Figure 18-1 on page shows a block diagram of the clock generation logic. ATmega165P 159) if the Buffer 160 ...
Page 161
... Input from XCK pin (internal Signal). Used for synchronous slave operation. Clock output to XCK pin (Internal Signal). Used for synchronous master operation. XTAL pin frequency (System Clock). contains equations for calculating the baud rate (in bits per second) and ATmega165P / DDR_XCK Figure 18-2 ...
Page 162
... The baud rate is defined to be the transfer rate in bit per second (bps) Baud rate (in bits per second, bps) System Oscillator clock frequency Contents of the UBRRnH and UBRRnL Registers, (0-4095) Figure 18-2 on page 161 depends on the stability of the system clock source therefore recommended to osc ATmega165P Equation for Calculating UBRR (1) f OSC UBRR = ...
Page 163
... Figure 18-4 on page 164 brackets are optional. 8019K–AVR–11/10 UCPOL = 1 XCK RxD/TxD UCPOL = 0 XCK RxD/TxD Figure 18-3 shows, when UCPOLn is zero the data will be changed illustrates the possible combinations of the frame formats. Bits inside ATmega165P Sample Sample 163 ...
Page 164
... – even ⊕ odd n 1 – Parity bit using even parity even odd Parity bit using odd parity Data bit n of the character n ATmega165P FRAME 4 [5] [6] [7] [8] [P] Sp1 [Sp2] … ⊕ ⊕ ⊕ ⊕ ⊕ ...
Page 165
... The following simple USART initialization code examples show one assembly and one C func- tion that are equal in functionality. The examples assume asynchronous operation using polling (no interrupts enabled) and a fixed frame format. The baud rate is given as a function parameter. 8019K–AVR–11/10 ATmega165P 165 ...
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... UCSR0C,r16 ret (1) ... USART_Init ( MYUBRR ); ... /* Set baud rate */ UBRR0H = (unsigned char)(ubrr>>8); UBRR0L = (unsigned char)ubrr; /* Enable receiver and transmitter */ UCSR0B = (1<<RXEN0)|(1<<TXEN0); /* Set frame format: 8data, 2stop bit */ UCSR0C = (1<<USBS0)|(3<<UCSZ00); 1. See “About Code Examples” on page 8. ATmega165P 166 ...
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... UCSR0A,UDRE0 rjmp USART_Transmit ; Put data (r16) into buffer, sends the data sts UDR0,r16 ret (1) /* Wait for empty transmit buffer */ while ( !( UCSR0A & (1<<UDRE0 Put data into buffer, sends the data */ UDR0 = data; 1. See “About Code Examples” on page 8. ATmega165P 167 ...
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... Put data into buffer, sends the data */ UDR0 = data; 1. These transmit functions are written to be general functions. They can be optimized if the con- tents of the UCSRnB is static. For example, only the TXB8n bit of the UCSRnB Register is used after initialization. 2. See “About Code Examples” on page 8. ATmega165P 168 ...
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... The disabling of the Transmitter (setting the TXENn to zero) will not become effective until ongo- ing and pending transmissions are completed, that is, when the Transmit Shift Register and Transmit Buffer Register do not contain data to be transmitted. When disabled, the Transmitter will no longer override the TxD pin. 8019K–AVR–11/10 ATmega165P 169 ...
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... UCSR0A, RXC0 rjmp USART_Receive ; Get and return received data from buffer in r16, UDR0 ret (1) /* Wait for data to be received */ while ( !(UCSR0A & (1<<RXC0 Get and return received data from buffer */ return UDR0; 1. See “About Code Examples” on page 8. ATmega165P 170 ...
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... FIFO and consequently the TXB8n, FEn, DORn and UPEn bits, which all are stored in the FIFO, will change. The following code example shows a simple USART receive function that handles both nine bit characters and the status bits. 8019K–AVR–11/10 ATmega165P 171 ...
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... Get status and 9th bit, then data */ /* from buffer */ status = UCSR0A; resh = UCSR0B; resl = UDR0 error, return - status & (1<<FE0)|(1<<DOR0)|(1<<UPE0) ) return -1; /* Filter the 9th bit, then return */ resh = (resh >> 1) & 0x01; return ((resh << resl); 1. “About Code Examples” on page ATmega165P 8. 172 ...
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... Error when received. If Parity Check is not enabled the UPEn bit will always be read zero. For compatibility with future devices, always set this bit to zero when writing to UCSRnA. For more details see 8019K–AVR–11/10 “Parity Bit Calculation” on page 164 ATmega165P and “Parity Checker” on page 174. 173 ...
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... The following code example shows how to flush the receive buffer. Assembly Code Example USART_Flush: C Code Example void USART_Flush( void ) { } Note: 8019K–AVR–11/10 (1) sbis UCSR0A, RXC0 ret in r16, UDR0 rjmp USART_Flush (1) unsigned char dummy; while ( UCSR0A & (1<<RXC0) ) dummy = UDR0; 1. See “About Code Examples” on page 8. ATmega165P 174 ...
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... Each of the samples is given a number that is equal to the state of the recovery unit. 8019K–AVR–11/10 RxD IDLE Sample (U2X = 0) Sample (U2X = 1) ATmega165P START Figure 18-6 on page 176 shows the sampling of the Figure 18-5 ...
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... RxD Sample (U2X = Sample (U2X = Figure 18-7. For Double Speed mode the first low level must be delayed to 177) base frequency, the Receiver will not be able to synchronize the ATmega165P BIT ...
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... Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (U2Xn = (%) R (%) slow fast 5 94.12 105.66 6 94.92 104.92 7 95.52 104,35 8 96.00 103.90 9 96.39 103.53 10 96.70 103.23 ATmega165P ( ) ----------------------------------- fast for normal speed and for normal speed and M Recommended Max Max Total Error (%) Receiver Error (%) +6.67/-6.8 ±3.0 +5.79/-5.88 ± ...
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... MPCMn bit in UCSRnA, otherwise it waits for the next address byte and keeps the MPCMn setting. 4. The addressed MCU will receive all data frames until a new address frame is received. The other Slave MCUs, which still have the MPCMn bit set, will ignore the data frames. 8019K–AVR–11/10 ATmega165P 178 ...
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... Kbps 230.4 Kbps ATmega165P Table 18-4. UBRR values “Asynchronous Operational ⎞ Closest Match • 100% – ⎠ 2.0000 MHz osc U2Xn = 0 Error UBRR Error UBRR 0.0% 51 0.2% 103 0.0% 25 0.2% 51 0.0% 12 0. ...
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... Kbps 0.5 Mbps ATmega165P f = 7.3728 MHz osc U2Xn = 0 U2Xn = 1 Error UBRR Error UBRR 0.2% 191 0.0% 383 0.2% 95 0.0% 191 0.2% 47 0.0% 95 -0.8% 31 0.0% 63 0.2% 23 0.0% 47 2.1% 15 0.0% 31 0.2% 11 0.0% 23 -3.5% 7 0.0% 15 -7.0% 5 0.0% 11 8.5% 3 0. ...
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... U2Xn = 0 Error UBRR Error UBRR -0.1% 287 0.0% 0.2% 143 0.0% 0.2% 71 0.0% 0.6% 47 0.0% 0.2% 35 0.0% -0.8% 23 0.0% 0.2% 17 0.0% 2.1% 11 0.0% 0.2% 8 0.0% -3.5% 5 0.0% 8.5% 2 0.0% 0.0% 2 -7.8% 0.0% – – 0.0% – – 1 Mbps 691.2 Kbps ATmega165P MHz f = 14.7456 MHz osc U2Xn = 1 U2Xn = 0 Error UBRR Error 575 0.0% 383 0.0% 287 0.0% 191 0.0% 143 0.0% 95 0.0% 95 0.0% 63 0.0% 71 0.0% 47 0.0% 47 0.0% 31 0.0% 35 0.0% 23 0.0% 23 0.0% 15 0.0% 17 0.0% 11 0.0% 11 0.0% 7 ...
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... Error UBRR Error UBRR 0.0% 479 0.0% -0.1% 239 0.0% 0.2% 119 0.0% -0.1% 79 0.0% 0.2% 59 0.0% 0.6% 39 0.0% 0.2% 29 0.0% -0.8% 19 0.0% 0.2% 14 0.0% 2.1% 9 0.0% -3.5% 4 0.0% 0.0% 4 -7.8% 0.0% – – 0.0% – – 2 Mbps 1.152 Mbps ATmega165P f = 20.0000 MHz osc U2Xn = 1 U2Xn = 0 Error UBRR Error 959 0.0% 520 0.0% 479 0.0% 259 0.2% 239 0.0% 129 0.2% 159 0.0% 86 -0.2% 119 0.0% 64 0.2% 79 0.0% 42 0.9% 59 0.0% 32 -1.4% 39 0.0% 21 -1.4% 29 0.0% 15 1.7% 19 0.0% 10 -1. ...
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... TXCIEn bit). 8019K–AVR–11/ RXBn[7:0] TXBn[7:0] R/W R/W R/W R RXCn TXCn UDREn FEn R R ATmega165P R/W R/W R/W R DORn UPEn U2Xn MPCMn R R R/W R UDRn (Read) UDRn (Write) UCSRnA ...
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... RXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the RXCn bit in UCSRnA is set. 8019K–AVR–11/10 “Multi-processor Communication Mode” on page RXCIEn TXCIEn UDRIEn RXENn R/W R/W R/W R ATmega165P 178 TXENn UCSZn2 RXB8n TXB8n R/W R UCSRnB 184 ...
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... Bit 6 – UMSELn: USART Mode Select This bit selects between asynchronous and synchronous mode of operation. Table 18-8. 8019K–AVR–11/ – UMSELn UPMn1 UPMn0 R R/W R UMSELn Bit Settings UMSELn Mode 0 Asynchronous Operation 1 Synchronous Operation ATmega165P USBSn UCSZn1 UCSZn0 R/W R/W R/W R UCPOLn UCSRnC R/W 0 185 ...
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... USBSn Stop Bit(s) 0 1-bit 1 2-bit UCSZn1 ATmega165P Parity Mode Disabled Reserved Enabled, Even Parity Enabled, Odd Parity UCSZn0 Character Size 0 5-bit 1 6-bit 0 7-bit 1 8-bit 0 Reserved 1 Reserved 0 Reserved 1 9-bit 186 ...
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... Falling XCK Edge – – – – UBRRn[7: R/W R/W R/W R ATmega165P Received Data Sampled (Input on RxD Pin) Falling XCK Edge Rising XCK Edge UBRRn[11: R/W R/W R/W R/W R/W R/W R/W R UBRRnH ...
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... Register Output and output pin, which delays the change of data output to the opposite clock edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin independent of the configuration. 8019K–AVR–11/10 “Pinout ATmega165P” on page 2. CPU accessible I/O Registers, including I/O bits 196 ...
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... USCK pin via the PORT Register or by writing a one to the USITC bit in USICR. 8019K–AVR–11/10 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 shows two USI units operating in Three-wire mode, one as Master and one as ATmega165P DO DI USCK DO DI USCK PORTxn 189 ...
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... USIDR,r16 ldi r16,(1<<USIOIF) sts USISR,r16 ldi r16,(1<<USIWM0)|(1<<USICS1)|(1<<USICLK)|(1<<USITC) sts USICR,r16 lds r16, USISR sbrs r16, USIOIF ATmega165P LSB LSB 19-3. At the top of the figure is a USCK cycle ref- ...
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... USICR,r16 ; MSB sts USICR,r17 sts USICR,r16 sts USICR,r17 sts USICR,r16 sts USICR,r17 sts USICR,r16 sts USICR,r17 sts USICR,r16 sts USICR,r17 sts USICR,r16 sts USICR,r17 sts USICR,r16 sts USICR,r17 sts USICR,r16 ; LSB sts USICR,r17 lds r16,USIDR ATmega165P 191 ...
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... Three-wire mode and positive edge Shift Register clock. The loop is repeated until the USI Counter Overflow Flag is set. 8019K–AVR–11/10 ldi r16,(1<<USIWM0)|(1<<USICS1) sts USICR,r16 sts USIDR,r16 ldi r16,(1<<USIOIF) sts USISR,r16 lds r16, USISR sbrs r16, USIOIF rjmp SlaveSPITransfer_loop lds r16,USIDR ret ATmega165P 192 ...
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... Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 shows two USI units operating in Two-wire mode, one as Master and one as Slave. ATmega165P VCC SDA SCL HOLD SCL Two-wire Clock Control Unit SDA SCL PORTxn 193 ...
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... S ADDRESS R/W ACK (Figure 19-5), a bus transfer involves the following steps: (Figure 19-6) detects the start condition and sets the USISIF SDA SCL ATmega165P DATA ACK DATA ACK USISIF CLOCK HOLD CLR CLR P F ...
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... The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe. 8019K–AVR–11/10 Figure 19-6 on page “Clock Systems and their Distribution” on page /4. This is also the maximum data transmit and CK ATmega165P 194. The SDA line is delayed (in 26) must also be taken 195 ...
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... A counter overflow interrupt will wakeup the processor from Idle sleep mode. 8019K–AVR–11/ MSB R/W R/W R/W R USISIF USIOIF USIPF USIDC R/W R/W R ATmega165P LSB R/W R/W R/W R USICNT3 USICNT2 USICNT1 USICNT0 R/W R/W R/W R USIDR ...
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... The relations between USIWM1..0 and the USI operation is summarized in 8019K–AVR–11/ USISIE USIOIE USIWM1 USIWM0 R/W R/W R/W R ATmega165P USICS1 USICS0 USICLK USITC R/W R Table 19-1 on page 198. ...
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... SCL line is also held low when a counter overflow occurs, and is held low until the Counter Overflow Flag (USIOIF) is cleared. 1. The DI and USCK pins are renamed to Serial Data (SDA) and Serial Clock (SCL) respectively to avoid confusion between the modes of operation. ATmega165P (1) . 198 ...
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... External, positive edge 1 0 External, negative edge 0 1 External, positive edge 1 1 External, negative edge ATmega165P 4-bit Counter Clock Source No Clock Software clock strobe (USICLK) Timer/Counter0 Compare Match External, both edges External, both edges Software clock strobe (USITC) Software clock strobe (USITC) Table 19-2) ...
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... ADC MULTIPLEXER OUTPUT Notes: 8019K–AVR–11/10 Figure 20-1. ACBG (1) 1. See Table 20-1 on page 201. 2. Refer to Figure 1-1 on page 2 and log Comparator pin placement. ATmega165P “PRR – Power Reduction Register” on page 41 (2) Section 12.3 “Alternate Port Functions” on page 67 must for Ana- 200 ...