ADAU1701JSTZ Analog Devices Inc, ADAU1701JSTZ Datasheet - Page 14

• Manufacturer Part Number: ADAU1701JSTZ
• Description: IC AUDIO PROC 2ADC/4DAC 48-LQFP
• Manufacturer: Analog Devices Inc
• Series: SigmaDSP®r
• Type: Audio Processorr

Specifications of ADAU1701JSTZ

• Design Resources: Analog Audio Input, Class-D Output with ADAU1701, SSM2306, and ADP3336 (CN0162)
• Applications: Automotive, Monitors, MP3
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Audio Control Type: Digital
• Control Interface: I2C, Serial
• Supply Voltage Range: 1.8V, 3.3V
• Operating Temperature Range: 0°C To +70°C
• Audio Ic Case Style: LQFP
• No. Of Pins: 48
• Svhc: No SVHC
• Control / Process Application: MP3 Player Speaker Docks, Automotive Head Units, Studio Monitors
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADAU1701MINIZ - BOARD EVAL SIGMADSP AUD ADAU1701EVAL-ADAU1701EBZ - BOARD EVAL FOR ADAU1701
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADAU1701
Pin No.
33
34
35
36, 48
38, 39
40
41
43 to 46
44
45
46
47
1
input/output.
PWR = power/ground, A_IN = analog input, D_IN = digital input, A_OUT = analog output, D_IO = digital input/output, D_IO/A_IO = digital input/output or analog
Mnemonic
PGND
PVDD
PLL_LF
AVDD
PLL_MODE0,
PLL_MODE1
CM
FILTD
VOUT3
VOUT2
VOUT1
VOUT0
FILTA
Type
PWR
PWR
A_OUT
PWR
D_IN
A_OUT
A_OUT
A_OUT
A_OUT
A_OUT
A_OUT
A_OUT
1
Description
PLL Ground Pin. The AGND, DGND, and PGND pins can be tied directly together in a
common ground plane. Decouple PGND to PVDD by using a 100 nF capacitor.
3.3 V Power Supply for the PLL and the Auxiliary ADC Analog Section. Decouple this pin to
PGND by using a 100 nF capacitor.
PLL Loop Filter Connection. Two capacitors and a resistor need to be connected to this pin, as
shown in Figure 15. See the Setting Master Clock/PLL Mode section for more details.
3.3 V Analog Supply. Decouple this pin to AGND by using a 100 nF capacitor.
PLL Mode Setting. PLL_MODE0 and PLL_MODE1 set the output frequency of the master
clock PLL. See the Setting Master Clock/PLL Mode section for more details.
1.5 V Common-Mode Reference. Connect a 47 μF decoupling capacitor between this pin and
ground to reduce crosstalk between the ADCs and DACs. The material of the capacitors is not
critical. This pin can be used to bias external analog circuits, as long as those circuits are not
drawing current from the pin (such as when CM is connected to the noninverting input of
an op amp).
DAC Filter Decoupling Pin. Connect a 10 μF capacitor between this pin and ground. The
capacitor material is not critical. The voltage on this pin is 1.5 V.
VOUT DAC Output. The full-scale output voltage is 0.9 V rms. This output can be used with
either an active or passive output reconstruction filter. See the Audio DACs section for details.
VOUT2 DAC Output. The full-scale output voltage is 0.9 V rms. This output can be used with
either an active or passive output reconstruction filter. See the Audio DACs section for details.
VOUT1 DAC Output. The full-scale output voltage is 0.9 V rms. This output can be used with
either an active or passive output reconstruction filter. See the Audio DACs section for details.
VOUT0 DAC Output. The full-scale output voltage is 0.9 V rms. This output can be used with
either an active or passive output reconstruction filter. See the Audio DACs section for details.
ADC Filter Decoupling Pin. A 10 μF capacitor should be connected between this pin and
ground. The capacitor material is not critical. The voltage on this pin is 1.5 V.
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