ADAU1701JSTZ Analog Devices Inc, ADAU1701JSTZ Datasheet - Page 8

• Manufacturer Part Number: ADAU1701JSTZ
• Description: IC AUDIO PROC 2ADC/4DAC 48-LQFP
• Manufacturer: Analog Devices Inc
• Series: SigmaDSP®r
• Type: Audio Processorr

Specifications of ADAU1701JSTZ

• Design Resources: Analog Audio Input, Class-D Output with ADAU1701, SSM2306, and ADP3336 (CN0162)
• Applications: Automotive, Monitors, MP3
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Audio Control Type: Digital
• Control Interface: I2C, Serial
• Supply Voltage Range: 1.8V, 3.3V
• Operating Temperature Range: 0°C To +70°C
• Audio Ic Case Style: LQFP
• No. Of Pins: 48
• Svhc: No SVHC
• Control / Process Application: MP3 Player Speaker Docks, Automotive Head Units, Studio Monitors
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADAU1701MINIZ - BOARD EVAL SIGMADSP AUD ADAU1701EVAL-ADAU1701EBZ - BOARD EVAL FOR ADAU1701
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADAU1701
REGULATOR
Table 7. Regulator
Parameter
DVDD Voltage
1
DIGITAL TIMING SPECIFICATIONS
Table 8. Digital Timing
Parameter
MASTER CLOCK
SERIAL PORT
SPI PORT
I
2
Regulator specifications are calculated using a Zetex Semiconductors FZT953 transistor in the circuit.
C PORT
t
t
t
t
t
t
t
t
t
t
t
t
f
t
t
t
t
t
t
t
t
f
t
t
t
t
t
t
t
t
t
t
MP
BIL
BIH
LIS
LIH
SIS
SIH
LOS
LOH
TS
SODS
SODM
CCLK
CCPL
CCPH
CLS
CLH
CLPH
CDS
CDH
COD
SCL
SCLH
SCLL
SCS
SCH
DS
SCR
SCF
SDR
SDF
BFT
1
1
t
36
48
73
291
40
40
10
10
10
10
10
10
80
80
0
100
80
0
80
0.6
1.3
0.6
0.6
100
0.6
MIN
Limit
t
244
366
488
1953
5
40
40
6.25
101
400
300
300
300
300
MAX
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
kHz
μs
μs
μs
μs
ns
ns
ns
ns
ns
Min
1.7
Test Conditions/Comments
MCLKI period, 512 × f
MCLKI period, 384 × f
MCLKI period, 256 × f
MCLKI period, 64 × f
INPUT_BCLK (Pin 9) low pulse width
INPUT_BCLK (Pin 9) high pulse width
INPUT_LRCLK (Pin 8) setup; time to INPUT_BCLK rising
INPUT_LRCLK (Pin 8) hold; time from INPUT_BCLK rising
SDATA_INx (Pin 10, Pin 11, Pin 28, or Pin 29) setup; time to INPUT_BCLK (Pin 9)
rising
SDATA_INx (Pin 10, Pin 11, Pin 28, or Pin 29) hold; time from INPUT_BCLK (Pin 9)
rising
OUTPUT_LRCLK (Pin 16) setup in slave mode
OUTPUT_LRCLK (Pin 16) hold in slave mode
OUTPUT_BCLK (Pin 11) falling to OUTPUT_LRCLK (Pin 16) timing skew
SDATA_OUTx (Pin 14, Pin 15, Pin 26, or Pin 27) delay in slave mode; time from
OUTPUT_BCLK (Pin 11) falling
SDATA_OUTx (Pin 14, Pin 15, Pin 26, or Pin 27) delay in master mode; time from
OUTPUT_BCLK (Pin 11) falling
CCLK (Pin 23) frequency
CCLK (Pin 23) pulse width low
CCLK (Pin 23) pulse width high
CLATCH (Pin 21) setup; time to CCLK (Pin 23) rising
CLATCH (Pin 21) hold; time from CCLK (Pin 23) rising
CLATCH (Pin 21) pulse width high
CDATA (Pin 20) setup; time to CCLK (Pin 23) rising
CDATA (Pin 20) hold; time from CCLK (Pin 23) rising
COUT (Pin 22) delay; time from CCLK (Pin 23) falling
SCL (Pin 23) frequency
SCL (Pin 23) high
SCL (Pin 23) low
Setup time, relevant for repeated start condition
Hold time; after this period, the first clock is generated
Data setup time
SCL (Pin 23) rise time
SCL (Pin 23) fall time
SDA (Pin 22) rise time
SDA (Pin 22) fall time
Bus-free time; time between stop and start
Rev. A | Page 8 of 56
Typ
1.8
S
S
S
S
mode
mode
mode
mode
Max
1.84
Unit
V