ADAU1701JSTZ Analog Devices Inc, ADAU1701JSTZ Datasheet - Page 38

• Manufacturer Part Number: ADAU1701JSTZ
• Description: IC AUDIO PROC 2ADC/4DAC 48-LQFP
• Manufacturer: Analog Devices Inc
• Series: SigmaDSP®r
• Type: Audio Processorr

Specifications of ADAU1701JSTZ

• Design Resources: Analog Audio Input, Class-D Output with ADAU1701, SSM2306, and ADP3336 (CN0162)
• Applications: Automotive, Monitors, MP3
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Audio Control Type: Digital
• Control Interface: I2C, Serial
• Supply Voltage Range: 1.8V, 3.3V
• Operating Temperature Range: 0°C To +70°C
• Audio Ic Case Style: LQFP
• No. Of Pins: 48
• Svhc: No SVHC
• Control / Process Application: MP3 Player Speaker Docks, Automotive Head Units, Studio Monitors
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADAU1701MINIZ - BOARD EVAL SIGMADSP AUD ADAU1701EVAL-ADAU1701EBZ - BOARD EVAL FOR ADAU1701
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADAU1701
2064 TO 2068 (0x0810 TO 0x0814)—SAFELOAD
DATA REGISTERS
Many applications require real-time microcontroller control of
signal processing parameters, such as filter coefficients, mixer
gains, multichannel virtualizing parameters, or dynamics
processing curves. When controlling a biquad filter, for
example, all of the parameters must be updated at the same
time. Doing so prevents the filter from executing with a mix of
old and new coefficients for one or two audio frames, thus
avoiding temporary instability and transients that may take a
long time to decay. To accomplish this, the ADAU1701 uses
safeload data registers to simultaneously load a set of five 28-bit
values to the desired parameter RAM address. Five registers are
used because a biquad filter uses five coefficients and, as
previously mentioned, it is desirable to do a complete update in
one transaction.
The first step in performing a safeload operation is writing the
parameter address to one of the safeload address registers (2069
to 2073). The 10-bit data-word to be written is the address in
parameter RAM to which the safeload is being performed. After
this address is written, the 28-bit data-word can be written to
the corresponding safeload data register (2064 to 2068).
The data formats for these writes are detailed in Table 30 and
Table 31. Table 39 shows how each of the five address registers
maps to its corresponding data register.
Table 40. Safeload Registers Bit Map
D31
D15
SD31
SD15
Table 41.
Bit Name
SD[39:0]
2069 TO 2073 (0x0815 TO 0x819)—SAFELOAD ADDRESS REGISTERS
Table 42. Safeload Address Registers Bit Map
D15
0
Table 43.
Bit Name
SA[11:0]
D30
D14
SD30
SD14
D14
0
D29
D13
SD29
SD13
D13
0
D12
0
D28
D12
SD28
SD12
D11
SA11
D27
D11
SD27
SD11
D10
SA10
D26
D10
SD26
SD10
Description
Safeload Data. Data (program, parameters, register contents) to be loaded into the RAMs or
registers.
Description
Safeload Address. Address of data that is to be loaded into the RAMs or registers
D9
SA09
D25
D9
SD25
SD09
D8
SA08
D24
D8
SD24
SD08
Rev. A | Page 38 of 56
D7
SA07
D39
D23
D7
SD39
SD23
SD07
D6
SA06
D38
D22
D6
SD38
SD22
SD06
After the address and data registers are loaded, set the initiate
safeload transfer bit in the core control register to initiate the
loading into RAM. Each of the five safeload registers takes one of
the 1024 core instructions to load into the parameter RAM. The
total program lengths should, therefore, be limited to 1019 cycles
(1024 minus 5) to ensure that the SigmaDSP core always has at
least five cycles available. The safeload is guaranteed to occur
within one LRCLK period (21 μs for a f
safeload transfer bit being set.
The safeload logic automatically sends data to be loaded into
RAM from only those safeload registers that have been written
to since the last safeload operation. For example, if two parameters
are to be updated in the RAM, only two of the five safeload registers
must be written. When the initiate safeload transfer bit is asserted,
only data from those two registers are sent to the RAM; the other
three registers are not sent to the RAM and may hold old or
invalid data.
Table 39. Safeload Address and Data Register Mapping
Safeload
Register
0
1
2
3
4
D5
SA05
D37
D21
D5
SD37
SD21
SD05
D4
SA04
D36
D20
D4
SD36
SD20
SD04
Safeload
Address Register
2069
2070
2071
2072
2073
D3
SA03
D35
D19
D3
SD35
SD19
SD03
D2
SA02
D34
D18
D2
SD34
SD18
SD02
S
of 48 kHz) of the initiate
D1
SA01
D33
D17
D1
SD33
SD17
SD01
Safeload
Data Register
2064
2065
2066
2067
2068
D0
SA00
D32
D16
D0
SD32
SD16
SD00
Default
0x0000
0x0000
0x0000
Default
0x00