ADAU1701JSTZ Analog Devices Inc, ADAU1701JSTZ Datasheet - Page 18

• Manufacturer Part Number: ADAU1701JSTZ
• Description: IC AUDIO PROC 2ADC/4DAC 48-LQFP
• Manufacturer: Analog Devices Inc
• Series: SigmaDSP®r
• Type: Audio Processorr

Specifications of ADAU1701JSTZ

• Design Resources: Analog Audio Input, Class-D Output with ADAU1701, SSM2306, and ADP3336 (CN0162)
• Applications: Automotive, Monitors, MP3
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Audio Control Type: Digital
• Control Interface: I2C, Serial
• Supply Voltage Range: 1.8V, 3.3V
• Operating Temperature Range: 0°C To +70°C
• Audio Ic Case Style: LQFP
• No. Of Pins: 48
• Svhc: No SVHC
• Control / Process Application: MP3 Player Speaker Docks, Automotive Head Units, Studio Monitors
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADAU1701MINIZ - BOARD EVAL SIGMADSP AUD ADAU1701EVAL-ADAU1701EBZ - BOARD EVAL FOR ADAU1701
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADAU1701
INITIALIZATION
This section details the procedure for properly setting up the
ADAU1701. The following five-step sequence provides an
overview of how to initialize the IC:
1.
2.
3.
4.
5.
To only test analog audio pass-through (ADCs to DACs), skip
Step 3 and Step 4 and use the default internal program.
POWER-UP SEQUENCE
The ADAU1701 has a built-in power-up sequence that
initializes the contents of all internal RAMs on power-up or
when the device is brought out of a reset. On the positive edge
of RESET , the contents of the internal program boot ROM are
copied to the internal program RAM memory, the parameter
RAM is filled with values (all 0s) from its associated boot ROM,
and all registers are initialized to 0s. The default boot ROM
program copies audio from the inputs to the outputs without
processing it (see
Input 0 and Input 1 are output on DAC0 and DAC1 and serial
digital Output 0 and Output 1. ADC0 and ADC1 are output on
DAC2 and DAC3. The data memories are also zeroed at power-
up. New values should not be written to the control port until
the initialization is complete.
Table 12. Power-Up Time
MCLKI Input
3.072 MHz (64 × f
11.289 MHz (256 × f
12.288 MHz (256 × f
18.432 MHz (384 × f
24.576 MHz (512 × f
The PLL start-up time lasts for 2
MCLKI pin. This time ranges from 10.7 ms for a 24.576 MHz
(512 × f
clock and is measured from the rising edge of RESET . Following
the PLL startup, the duration of the ADAU1701 boot cycle is about
42 μs for a f
from the ADAU1701 during this start-up time. For an MCLK input
of 12.288 MHz, the full initialization sequence (PLL startup plus
boot cycle) is approximately 21 ms. As the device comes out of a
reset, the clock mode is immediately set by the PLL_MODE0 and
PLL_MODE1 pins. The reset is synchronized to the falling edge
of the internal clock.
Apply power to ADAU1701.
Wait for PLL to lock.
Load SigmaDSP program and parameters.
Set up registers (including multipurpose pins and digital
interfaces).
Turn off the default muting of the converters, clear the
data registers, and initialize the DAC setup register (see
the Control Registers Setup section for specific settings).
S
) input clock to 85.3 ms for a 3.072 MHz (64 × f
S
of 48 kHz. The user should avoid writing to or reading
S
Figure 13
)
S
S
S
S
)
)
)
)
Init.
Time
85 ms
23 ms
21 ms
16 ms
11 ms
). In this program, serial digital
18
Max Program/
Parameter/Register
Boot Time (I
175 ms
175 ms
175 ms
175 ms
175 ms
cycles of the clock on the
2
C)
S
) input
Total
260 ms
198 ms
196 ms
191 ms
186 ms
Rev. A | Page 18 of 56
Table 12 lists typical times to boot the ADAU1701 into an
operational state of an application, assuming a 400 kHz I
clock loading a full program, parameter set, and all registers
(about 8.5 kB). In reality, most applications do not fill the RAMs
and therefore boot time (Column 3 of Table 12) is less.
CONTROL REGISTERS SETUP
The following registers must be set as described in this section
to initialize the ADAU1701. These settings are the basic minimum
settings needed to operate the IC with an analog input/output of
48 kHz. More registers may need to be set, depending on the
application. See the RAMs and Registers section for additional
settings.
DSP Core Control Register (Address 2076)
Set Bits[4:2] (ADM, DAM, and CR) each to 1.
DAC Setup Register (Address 2087)
Set Bits[0:1] (DS[1:0]) to 01.
RECOMMENDED PROGRAM/PARAMETER
LOADING PROCEDURE
When writing large amounts of data to the program or para-
meter RAM in direct write mode, the processor core should
be disabled to prevent unpleasant noises from appearing in
the audio output.
1.
2.
3.
4.
5.
POWER REDUCTION MODES
Sections of the ADAU1701 chip can be turned on and off as
needed to reduce power consumption. These include the ADCs,
DACs, and voltage reference.
The individual analog sections can be turned off by writing to
the auxiliary ADC and power control register. By default, the
ADCs, DACs, and reference are enabled (all bits set to 0). Each
of these can be turned off by writing a 1 to the appropriate bits
Set Bit 3 and Bit 4 (active low) of the core control register
to 1 to mute the ADCs and DACs. This begins a volume
ramp-down.
Set Bit 2 (active low) of the core control register to 1. This
zeroes the SigmaDSP accumulators, the data output registers,
and the data input registers.
Fill the program RAM using burst mode writes.
Fill the parameter RAM using burst mode writes.
Deassert Bit 2 to Bit 4 of the core control register.
SDATA_IN0
Figure 13. Default Program Signal Flow
ADC0
ADC1
DAC0
DAC1
DAC2
DAC3
SDATA_OUT0
2
C