TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 162

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

BR0ADD
(0203H)
(0204H)
BR0CR
0
1
+ (16 − K)/16 division enable
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
BR0ADD
<BR0K3:0>
Disable
Enable
1111 (K = 15)
0001 (K = 1)
Note1:Availability of +(16-K)/16 division function
Note2:Set BR0CR <BR0ADDE> to 1 after setting K (K = 1 to 15) to BR0ADD<BR0K3:0> when +(16-K)/16 division
Figure 3.9.14 Baud Rate Generator Control (Channel 0, BR0CR, BR0ADD)
0000
to
BR0CR
<BR0S3:0>
function is used. Writes to unused bits in the BR0ADD register do not affext operation, and undefined data is
read from these unused bits.
Always
write “0”.
The baud rate generator can be set “1” in UART mode and disable +(16-K)/16 division function.Don’t use in
I/O interface mode.
N
2 to 15
1 , 16
Sets baud rate generator frequency divisor
7
−
0
7
0000 (N = 16)
0001 (N = 1)
+ (16 − K)/16
division
0: Disable
1: Enable
BR0ADDE
BR0CR<BR0ADDE> = 1
Disable
Disable
6
0
6
or
UART mode
○
×
00: φT0
01: φT2
10: φT8
11: φT32
00
01
10
11
BR0CK1
Setting the input clock of baud rate generator
1111 (N = 15)
N + (16 − K)/16
0010 (N = 2)
Divided by
5
0
5
Disable
91C820A-160
Internal clock φT0
Internal clock φT2
Internal clock φT8
Internal clock φT32
to
BR0CK0
I/O mode
4
4
0
×
×
BR0CR<BR0ADDE> = 0
0001 (N = 1) (Only UART)
R/W
1111 (N = 15)
0000 (N = 16)
Divided by N
BR0S3
BR0K3
3
0
3
0
to
Setting of the divided frequency “N”
(Divided by N + (16 − K)/16)
Sets frequency divisor “K”
BR0S2
BR0K2
2
0
2
0
(0 to F)
R/W
BR0S1
BR0K1
1
0
1
0
BR0S0
BR0K0
TMP91C820A
0
0
0
0
2008-02-20