TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 204

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

<SIOS>
<SIOF>
<SEF>
SCK pin (Output)
SI pin
INTSBI interrupt
request
SBI0DBR
c.
Note: When the transfer mode is changed, the contents of SBI0DBR will be lost. If the
8-bit transmit/receive mode
After the data has been written, set SBI0CR<SIOS> to 1 to start
transmitting/receiving. When data is transmitted, the data is output via the SO
pin, starting from the least significant bit (LSB) and synchronized with the
leading edge of the serial clock signal. When data is received, the data is input via
the SI pin on the trailing edge of the serial clock signal. 8-bit data is transferred
from the shift register to SBI0DBR and an INTSBI interrupt request is generated.
The interrupt service program reads the received data from the data buffer
register and writes the data which is to be transmitted. SBI0DBR is used for both
transmitting and receiving. Transmitted data should always be written after
received data has been read.
until the received data has been read and the next data has been written.
the external clock, received data is read and transmitted data is written before a
new shift operation is executed. The maximum transfer speed when an external
clock is used is determined by the delay time between the time when an interrupt
request is generated and the time at which received data is read and transmitted
data is written.
SO pin holds final bit of the last data until falling edge of the SCK.
interrupt service program or when SBI0CR1<SIOINH> is set to 1. When <SIOS>
is cleared to 0, received data is transferred to SBI0DBR in complete blocks. The
transmit/receive mode ends when the transfer is complete. In order to confirm
whether data is being transmitted/received properly by the program; set SBI0SR
to be sensed. <SIOF> is set to 0 when transmitting/receiving has been completed.
When <SIOINH> is set to 1, data transmitting/receiving stops. <SIOF> is then
cleared to 0.
Figure 3.10.28 Receiver Mode (Example: Internal clock)
Set a control register to a transmit/receive mode and write data to SBI0DBR.
When an internal clock is used, the automatic wait function will be in effect
When an external clock is used, since the shift operation is synchronized with
When the transmit is started, after the SBI0SR<SIOF> goes 1 output from the
Transmitting/receiving data ends when <SIOS> is cleared to 0 by the INTSBI
a
0
mode must be changed, conclude data transmitting/receiving by clearing
<SIOS> to 0, read the last data, then change the transfer mode.
a
1
a
2
a
3
a
91C820A-202
4
a
5
a
6
a
Read receiver data
7
a
b
0
b
1
b
2
b
3
Clear <SIOS>
b
4
b
5
b
6
Read receiver data
b
TMP91C820A
7
2008-02-20
b