TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 201

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

(2) Transfer modes
mode.
a.
The SBI0CR1<SIOM1:0> is used to select a transmit, receive or transmit/receive
8-bit transmit mode
SBI0DBR.
transfer. The transmitted data is transferred from SBI0DBR to the shift register
and output to the SO pin in synchronized with the serial clock, starting from the
least significant bit (LSB), When the transmission data is transferred to the shift
register, the SBI0DBR becomes empty. An INTSBI (Buffer empty) interrupt
request is generated to request new data.
function will be initiated if new data is not loaded to the data buffer register after
the specified 8-bit data is transmitted. When new transmit data is written,
automatic-wait function is canceled.
data is shifted. The transfer speed is determined by the maximum delay time
between the time when an interrupt request is generated and the time when data
is written to SBI0DBR by the interrupt service program.
SO pin holds final bit of the last data until falling edge of the SCK.
interrupt service program or setting the <SIOINH> to 1. When the <SIOS> is
cleared, the transmitted mode ends when all data is output. In order to confirm if
data is surely transmitted by the program, set the <SIOF> (Bit3 of SBI0SR) to be
sensed. The SBI0SR<SIOF> is cleared to 0 when transmitting is complete. When
the <SIOINH> is set to 1, transmitting data stops. SBI0SR<SIOF> turns 0.
before new data is shifted; otherwise, dummy data is transmitted and operation
ends.
Set a control register to a transmit mode and write transmit data to the
After the transmit data is written, set the SBI0CR1<SIOS> to 1 to start data
When the internal clock is used, the serial clock will stop and automatic-wait
When the external clock is used, data should be written to SBI0DBR before new
When the transmit is started, after the SBI0SR<SIOF> goes 1 output from the
Transmitting data is ended by clearing the <SIOS> to 0 by the buffer empty
When an external clock is used, it is also necessary to clear SBI0SR<SIOS> to 0
91C820A-199
TMP91C820A
2008-02-20