TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 253

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

LCDCTL
(04B3H)
LCDFFP
(04B4H)
LCDDVM
(04B1H)
3.14.4.5 Frame Signal Settlement
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
value set in f
usually outputs the signal inverts polarity every frame period.
polarity irrelevant to above frame frequency for the purpose of preventing the patches
of display.
TMP91C820A defines so called frame period (Refresh interval for LCD panel) by the
And TMP91C820A has a special function that can set the timing of inverting frame
port
0: Display
1: Display
DOFF
LCDON
OFF
ON
FMN7
R/W
FP7
7
7
7
0
Setting all
column
ports to 0
0: Normal
1: All
FP
display
data 0
FMN6
ALL0
R/W
FP6
6
6
6
0
[9:0]. DLEBCD pin outputs pulse every frame period. DLEBFR pin
Divided FR
mode
0: Disable
1: Enable
FRMON
LCD Control Register
Divide FRM Register
FMN5
R/W
FP5
LCD f
5
5
5
0
91C820A-251
FP
Always
write “0”.
Setting bit7 to bit0 for f
Setting DVM bit7 to bit0
FMN4
Register
R/W
FP4
4
4
4
−
0
R/W
R/W
0
0
Setting bit9
for f
FMN3
FP
R/W
FP9
FP3
3
3
3
0
[9:0]
FP
Specify
address of
LCD driver
with built-in
RAM
0: OFF
1: ON
MMULCD
FMN2
R/W
FP2
2
2
2
0
Setting
bit8 for
f
FP
FMN1
FP8
R/W
FP1
[9:0]
1
1
1
0
TMP91C820A
Start
control in
SR mode
0: Stop
1: Start
START
FMN0
R/W
2008-02-20
FP0
0
0
0
0