TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 219

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TMP91xy20AFG

Manufacturer Part Number
TMP91xy20AFG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP91xy20AFG

Package
LQFP144
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
M
Rom Combinations
8
Ram Combinations
8
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
1
I2c/sio Bus Channels
1
(s)dram Controller
1
Adc 10-bit Channel
8
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
1
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
77
Power Supply Voltage(v)
3.0 to 3.6
(0301H)
Prohibit
read-
modify-
write
WDCR
WDMOD
(0300H)
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Selection <SYSCK>
Watchdog timer detection time
System Clock
SYSCR1
1 (fs)
0 (fc)
WDT
control
1: Enable
B1H: WDT disable code
4EH: WDT clear code
WDTE
R/W
7
7
1
Figure 3.12.5 Watchdog Timer Control Register
Figure 3.12.4 Watchdog Timer Mode Register
Select detecting time
00: 2
01: 2
10: 2
11: 2
WDTP1
6
15
17
19
21
<GEAR2:0>
6
0
Gear Value
100 (fc/16)
001 (fc/2)
010 (fc/4)
011 (fc/8)
/f
/f
/f
/f
SYSCR1
000 (fc)
SYS
SYS
SYS
SYS
XXX
R/W
WDTP0
91C820A-217
5
5
0
14.56 ms
29.13 ms
1.82 ms
3.64 ms
7.28 ms
2.00 s
4
4
00
W
Watchdog Timer Detection Time
Watchdog timer out control
Watchdog timer enable/disable control
IDLE2 Control
3
3
116.51 ms
0
1
0
1
0
1
14.56 ms
29.13 ms
58.25 ms
Others
B1H
4EH
8.00 s
7.28 ms
WDMOD<WDTP1:0>
01
Connects WDT out to a reset
Stop
Operation
Disabled
Enabled
Disable/clear WDT
IDLE2
0: Stop
1: Operate
I2WDT
2
2
0
Disable code
Clear code
Don’t care
at fc = 36 MHz, fs = 32.768 kHz
116.51 ms
233.02 ms
466.03 ms
32.00 s
29.13 ms
58.25 ms
R/W
1: Internally
10
connects
WDL out
to the
reset pin
RESCR
1
1
0
TMP91C820A
1864.14 ms
2008-02-20
128.00 s
116.51 ms
233.02 ms
466.03 ms
932.07 ms
Always
write “0”.
0
11
R/W
0
0

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