TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 63

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

P0
P0
(0000H)
(0000H)
P0CR
(0002H)
3.5.1
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Function
Note 1: Read-modify-write is prohibited for P0CR.
Note 2: When functioning as a data bus (D0 to D7), P0CR is cleared to 0.
Port 0 (P00 to P07)
output using the control register P0CR. Resetting resets all bits of the output latch P0, the
control register P0CR to 0 and sets port 0 to input mode. In addition to functioning as a
general-purpose I/O port, port 0 can also function as an data bus (D0 to D7).
to D7) and all bits of P0CR are cleared to 0.
Port 0 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or
When external memory is accesed, the port automatically functions as the data bus (D0
D0 to D7
Direction control
Output latch
(on bit basis)
P07C
P0CR write
P0 write
P07
7
7
0
Reset
External access (Data read)
P06C
P06
6
6
0
Data from external port (Output latch register is cleared to 0.)
Figure 3.5.2 Register for Port 0
P0 read
A
B
Selector
S
Figure 3.5.1 Port 0
Port 0 Control Register
P05C
P05
5
5
0
91C820A-61
Port 0 Register
Port 0 input/output settings
Output buffer
0: Input 1:Output
P04C
P04
4
4
0
R/W
W
External access (Data write)
External access
P03C
P03
3
3
0
P02C
P02
P00 to P07
2
2
0
(D0 to D7)
P01C
P01
1
1
0
TMP91C820A
P00C
2008-02-20
P00
0
0
0