FAN5099 Fairchild Semiconductor, FAN5099 Datasheet - Page 11

• Manufacturer Part Number: FAN5099
• Description: PWM and ULDO Controller Combo
• Manufacturer: Fairchild Semiconductor

FAN5099 Rev. 1.0.1
© 2006 Fairchild Semiconductor Corporation
PWM Operation
Refer to Figure 21 for the PWM control mechanism. The
FAN5099 uses the summing mode method of control to
generate the PWM pulses. The amplified output of the
current-sense amplifier is summed with an internally
generated ramp and the combined signal is amplified
and compared with the output of the error amplifier to get
the pulse width to drive the high-side MOSFET. The
sensed current from the previous cycle is used to modu-
late the output of the summing block. The output of the
summing block is also compared against the voltage
threshold set by the R
rent on a cycle-by-cycle basis. The controller facilitates
external compensation for enhanced flexibility.
Initialization
When the PWM is disabled, the SW node is connected
to GND through an internal 500Ω MOSFET to slowly dis-
charge the output. As long as the PWM controller is
enabled, this internal MOSFET remains OFF.
Soft-Start (PWM and LDO)
When V
the circuit releases SS and enables the PWM regulator.
The capacitor connected to the SS pin and GND is
charged by a 10µA internal current source, causing the
voltage on the capacitor to rise. When this voltage
exceeds 1.2V, all protection circuits are enabled. When
this voltage exceeds 2.2V, the LDO output is enabled.
The input to the error amplifier at the non-inverting pin is
clamped by the voltage on the SS pin until it crosses the
reference voltage.
The time it takes the PWM output to reach regulation
(T
Oscillator Clock Frequency (PWM)
The clock frequency on the oscillator is set using an
external resistor, connected between R(T) pin and
ground. The frequency follows the graph, as shown in
Figure 18. The minimum clock frequency is 50kHz,
which is when R(T) pin is left open. Select the value of
R(T) as shown in the equation below. This equation is
valid for all F
where, F
For example, for F
R
The FAN5099 provides for input voltage feed-forward
compensation through R
T
R t ( )
RISE
RAMP
Rise
) is calculated using the following equation:
=
=
CC
----------------------------------------------------------------- - kΩ
6.25
Selection and Feed-Forward Operation
OSC
8 10
exceeds the UVLO threshold and EN is high,
×
OSC
×
is in Hz.
F
–
OSC
2
4
> 50kHz.
×
OSC
×
C
10
–
LIM
SS
2.99 10
= 80kHz, R(t) = 199kΩ.
7
RAMP
resistor to limit the inductor cur-
(C
×
SS
. The value of R
is in μ f)
5
RAMP
(EQ. 1)
(EQ. 2)
effec-
11
tively changes the slope of the internal ramp, minimizing
the variation of the PWM modulator gain when input volt-
age varies. The R
explained in later sections. The R
approximated using the following equation:
where F
V
Gate Drive Section
The adaptive gate control logic translates the internal
PWM control signal into the MOSFET gate drive signals
and provides necessary amplification, level shifting, and
shoot-through protection. It also has functions that help
optimize the IC performance over a wide range of oper-
ating conditions. Since the MOSFET switching time can
vary dramatically from device to device and with the
input voltage, the gate control logic provides adaptive
dead time by monitoring the gate-to-source voltages of
both upper and lower MOSFETs. The lower MOSFET
drive is not turned on until the gate-to-source voltage of
the upper MOSFET has decreased to less than approxi-
mately 1V. Similarly, the upper MOSFET is not turned on
until the gate-to-source voltage of the lower MOSFET
has decreased to less than approximately 1V. This
allows a wide variety of upper and lower MOSFETs to be
used without a concern for simultaneous conduction, or
shoot-through.
A low impedance path between the driver pin and the
MOSFET gate is recommended for the adaptive dead-
time circuit to work properly. Any delay along this path
reduces the delay generated by the adaptive dead-time
circuit, thereby increasing the chances for shoot-through.
Protection
In the FAN5099, the converter is protected against over-
load, short-circuit, over-voltage, and under-voltage con-
ditions. All of these extreme conditions generate an
internal “fault latch” which shuts down the converter. For
all fault conditions, both the high-side and the low-side
drives are off, except in the case of OVP, where the low-
side MOSFET is turned on until the voltage on the FB pin
goes below 0.4V. The fault latch can be reset either by
toggling the EN pin or recycling VCC to the chip.
Over Current Limit (PWM)
The PWM converter is protected against overloading
through a cycle-by-cycle current limit set by selecting
R
threshold voltage for the output of the summing amplifier.
When the summing amplifier output exceeds this thresh-
old level, the current limit comparator trips and the PWM
starts skipping pulses. If the current limit tripping occurs
for 16 continuous clock cycles, a fault latch is set and the
R
IN
ILIM
RAMP
= 12V, R
resistor. An internal 10µA current source sets the
OSC
=
------------------------------------------- - KΩ
6.3
is in Hz. For example, for F
RAMP
V
(
IN nom
×10
,
= 2MΩ.
–
8
RAMP
×
)
–
F
1.8
OSC
effect on the current limit is
RAMP
OSC
value can be
www.fairchildsemi.com
= 80kHz and
(EQ. 3)