FAN5099 Fairchild Semiconductor, FAN5099 Datasheet - Page 14

• Manufacturer Part Number: FAN5099
• Description: PWM and ULDO Controller Combo
• Manufacturer: Fairchild Semiconductor

FAN5099 Rev. 1.0.1
© 2006 Fairchild Semiconductor Corporation
ceramic capacitors for the output; although lower ESR
can be achieved easily, higher capacitance values are
required to meet the V
transient. From the stability point of view, the zero
caused by the ESR of the output capacitor plays an
important role in the stability of the converter.
Output Capacitor Selection (LDO)
For stable operation, the minimum capacitance of 100µF
with ESR around 100mΩ is recommended. For other val-
ues, contact the factory.
Power MOSFET Selection (PWM)
The FAN5099 is capable of driving N-Channel MOSFETs
as circuit switch elements. For better performance, MOS-
FET selection should address these key parameters:
■
■
■
In typical applications for a buck converter, the duty
cycles are lower than 20%. To optimize the selection of
MOSFETs for both the high-side and low-side, follow dif-
ferent selection criteria. Select the high-side MOSFET to
minimize the switching losses and the low-side MOSFET
to minimize the conduction losses due to the channel
and the body diode losses. Note that the gate drive
losses also affect the temperature rise on the controller.
For loss calculation, refer to Fairchild's Application Note
AN-6005 and the associated spreadsheet.
High-Side Losses
Losses in the MOSFET can be understood by following
the switching interval of the MOSFET, as shown in Fig-
ure 23. The MOSFET gate drive equivalent circuit is
shown in Figure 24.
The maximum Drain-to-Source Voltage (V
at least 25% higher than the worst-case input voltage.
The MOSFETs should have low Q
The R
Figure 23. Switching Losses and Q
DS_ON
of the MOSFETs should be as low as possible.
OUT(MIN)
restrictions during a load
G
, Q
GD
,
and Q
DS
) should be
GS
G
.
14
The upper graph in Figure 23 represents Drain-to-
Source Voltage (V
The lower graph details Gate-to-Source Voltage (V
versus time with a constant current charging the gate.
The x-axis is representative of Gate Charge (Q
C
receives current from the gate driver during t3 (as VDS is
falling). Obtain the gate charge (Q
on the lower graph from the MOSFET datasheets.
Assuming switching losses are about the same for both
the rising edge and falling edge, Q1's switching losses
occur during the shaded time when the MOSFET has
voltage across it and current through it.
Losses are given by (EQ. 9), (EQ. 10), and (EQ. 11):
P
where P
P
for a given MOSFET R
temperature (T
fall time) and equals t2+t3 (Figure 23.).
The driver's impedance and C
period is controlled by the driver's impedance and Q
Since most of t
stant current for the driver to simplify the calculation of t
with the following equation:
Most MOSFET vendors specify Q
can be determined as:
Q
charge required to reach the MOSFET threshold (V
Note that for the high-side MOSFET, V
which can be as high as 20V in a typical portable appli-
cation. Include the power delivered to the MOSFET's
P
P
t
s
UPPER
SW
GD
G(SW)
SW
COND
=
and P
Q
------------------- -
+ C
=
I
Driver
G SW
Figure 24. Drive Equivalent Circuit
= P
⎛
⎝
=
UPPER
= Q
(
V
---------------------
GS
⎛
⎝
COND
DS
SW
V
--------------
)
GD
2
V
OUT
≈
and controls t1, t2, and t4 timing. C
×
IN
S
+ P
J
is the upper MOSFET's total losses and
--------------------------------------------- -
⎛
⎝
I
) and t
L
----------------------------------------
R
+ Q
are the switching and conduction losses
occurs when V
⎞
⎠
DS
×
Driver
COND
V
×
2 t
Q
) and Drain Current (I
CC
GS
I
OUT
×
2
G SW
DS(ON)
S
(
–
+
s
– Q
⎞ F
⎠
is the switching period (rise or
V
R
×
SP
)
Gate
SW
R
TH
DS ON
is at the maximum junction
ISS
GS
⎞
⎠
where Q
(
determine t2 while t3's
G
= V
GD
) parameters shown
)
SP,
and Q
DS
TH
assume a con-
D
www.fairchildsemi.com
) waveforms.
equals V
GS
is the gate
G
. Q
). C
(EQ. 10)
(EQ. 12)
(EQ. 11)
(EQ. 9)
G(SW)
TH
ISS
GD
GS
).
GD
IN
.
S
=
)
,