FAN5099 Fairchild Semiconductor, FAN5099 Datasheet - Page 18

• Manufacturer Part Number: FAN5099
• Description: PWM and ULDO Controller Combo
• Manufacturer: Fairchild Semiconductor

FAN5099 Rev. 1.0.1
© 2006 Fairchild Semiconductor Corporation
Design Tools
Fairchild application note AN-6020 provides a PSPICE
model and spreadsheet calculator for the PWM regula-
tor, simplifying external component selections and verify-
ing loop stability. The topics covered in the datasheet
provide an understanding behind the calculations in the
spreadsheet.
The spreadsheet calculator, which is part of AN-6020
can be used to calculate all external component values
for designing around FAN5099. The spreadsheet pro-
vides optimized compensation components and gener-
ates a Bode plot to ensure loop stability.
Based on the input values entered, AN-6020’s PSPICE
model can be used to simulate Bode plots (for loop sta-
bility) as well as transient analysis that help customize
the design for a wide range of applications.
Use Fairchild application note AN-6005 for prediction of
the losses and die temperatures for the power semicon-
ductors used in the circuit.
Both AN-6020 and AN-6005 can be downloaded from
www.fairchildsemi.com/apnotes/.
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Layout Considerations
The switching power converter layout needs careful
attention and is critical to achieving low losses and clean
and stable operation. Below are specific recommenda-
tions for a good board layout:
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Keep the high current traces and load connections as
short as possible.
Use thick copper boards whenever possible to
achieve higher efficiency.
Keep the loop area between the SW node, low-side
MOSFET, inductor, and the output capacitor as small
as possible.
Route high dV/dt signals, such as SW node, away
from the error amplifier input/output pins. Keep com-
ponents connected to these pins close to the pins.
Place ceramic de-coupling capacitors very close to
VCC pin.
All input signals are referenced with respect to AGND
pin. Dedicate one layer of the PCB for a GND plane.
Use at least 4 layers for the PCB.
Minimize GND loops in the layout to avoid EMI-related
issues.
Use wide traces for the lower gate drive to keep the
drive impedances low.
Connect PGND directly to the lower MOSFET source
pin.
Use wide land areas with appropriate thermal vias to
effectively remove heat from the MOSFETs.
Use snubber circuits to minimize high-frequency
ringing at the SW nodes.
Place the output capacitor for the LDO close to the
source of the LDO MOSFET.
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