DS2148

Manufacturer Part NumberDS2148
Description5V E1/T1/J1 Line Interface
ManufacturerDallas Semiconducotr
DS2148 datasheet
 


1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Page 1/75

Download datasheet (545Kb)Embed
Next
www.maxim-ic.com
FEATURES
§ Complete E1, T1, or J1 line interface unit
(LIU)
§ Supports both long- and short-haul trunks
§ Internal software-selectable receive-side
termination for 75Ω/100Ω/120W
§ 5V power supply
§ 32-bit or 128-bit crystal-less jitter attenuator
requires only a 2.048MHz master clock for
both E1 and T1 with option to use 1.544MHz
for T1
§ Generates the appropriate line build outs,
with and without return loss, for E1 and
DSX-1 and CSU line build outs for T1
§ AMI, HDB3, and B8ZS, encoding/decoding
§ 16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz clock output synthesized to
recovered clock
§ Programmable monitor mode for receiver
§ Loopbacks and PRBS pattern generation/
detection with output for received errors
§ Generates/detects in-band loop codes, 1 to 16
bits including CSU loop codes
§ 8-bit parallel or serial interface with optional
hardware mode
§ Multiplexed and nonmultiplexed parallel bus
supports Intel or Motorola
§ Detects/generates blue (AIS) alarms
§ NRZ/bipolar interface for TX/RX data I/O
§ Transmit open-circuit detection
§ Receive Carrier Loss (RCL) indication
(G.775)
§ High-Z State for TTIP and TRING
§ 50mA (rms) current limiter
DS2148/DS21Q48
5V E1/T1/J1 Line Interface
PIN DESCRIPTION
44
1
44 TQFP
7mm
CABGA
ORDERING INFORMATION
Single-Channel Devices:
DS2148TN
44-Pin TQFP
DS2148T
44-Pin TQFP
DS2148GN
7mm CABGA (-40°C to +85°C)
DS2148G
7mm CABGA (0
Four-Channel Devices:
DS21Q48N
(Quad) BGA
DS21Q48
(Quad) BGA
1 of 75
(-40°C to +85°C)
o
o
(0
C to +70
C)
o
o
C to +70
C)
(-40°C to +85°C)
o
o
(0
C to +70
C)
REV: 082504

DS2148 Summary of contents

  • Page 1

    ... PIN DESCRIPTION TQFP 7mm CABGA ORDERING INFORMATION Single-Channel Devices: DS2148TN 44-Pin TQFP DS2148T 44-Pin TQFP DS2148GN 7mm CABGA (-40°C to +85°C) DS2148G 7mm CABGA (0 Four-Channel Devices: DS21Q48N (Quad) BGA DS21Q48 (Quad) BGA (-40°C to +85° +70 C) ...

  • Page 2

    ... T1 applications). The jitter attenuator FIFO is selectable to either 32 bits or 128 bits in depth and can be placed in either the transmit or receive data paths 2.048MHz output clock synthesized to RCLK is available for use as a backplane system clock (where 8). The DS2148 has diagnostic capabilities such as loopbacks and PRBS pattern generation/detection. 16-bit loop-up and loop-down codes can be generated and detected ...

  • Page 3

    LIST OF FIGURES............................................................................................................................... 4 2. LIST OF TABLES ................................................................................................................................ 5 3. INTRODUCTION................................................................................................................................. 6 3.1 DOCUMENT REVISION HISTORY ............................................................................................ 6 4. PIN DESCRIPTION ............................................................................................................................. 9 5. HARDWARE MODE ......................................................................................................................... 22 5.1 REGISTER MAP .......................................................................................................................... 23 5.2 PARALLEL PORT OPERATION................................................................................................ 24 ...

  • Page 4

    ... LIST OF FIGURES Figure 3-1 DS2148 BLOCK DIAGRAM..................................................................................................... 7 Figure 3-2 RECEIVE LOGIC ...................................................................................................................... 8 Figure 3-3 TRANSMIT LOGIC ................................................................................................................... 9 Figure 4-1 PARALLEL PORT MODE PINOUT (BIS1 = 0, BIS0 = ............................................ 21 Figure 4-2 SERIAL PORT MODE PINOUT (BIS1 = 1, BIS0 = 0) .......................................................... 21 Figure 4-3 HARDWARE MODE PINOUT (BIS1 = 1, BIS0 = 1) ............................................................ 22 Figure 5-1 SERIAL PORT OPERATION FOR READ ACCESS (R=1) MODE 1.................................. 25 Figure 5-2 SERIAL PORT OPERATION FOR READ ACCESS MODE 2 ...

  • Page 5

    ... Table 4-2a PIN ASSIGNMENT................................................................................................................. 10 Table 4-2b PIN DESCRIPTIONS (Sorted by Pin Name, DS2148T Pin Numbering) ............................... 11 Table 4-3a PIN ASSIGNMENT IN SERIAL PORT MODE..................................................................... 13 Table 4-3b PIN DESCRIPTIONS IN SERIAL PORT MODE (Sorted by Pin Name, DS2148T Pin Numbering) .......................................................................................................................................... 14 Table 4-4a PIN ASSIGNMENT IN HARDWARE MODE....................................................................... 16 Table 4-4b PIN DESCRIPTIONS IN HARDWARE MODE (Sorted by Pin Name, DS2148T Pin Numbering) ...

  • Page 6

    ... Data input at TPOS and TNEG is sent via the jitter attenuation MUX to the waveshaping circuitry and line driver. The DS2148 will drive the line from the TTIP and TRING pins via a coupling transformer. The line driver can handle both CEPT 30/ISDN-PRI lines for E1 and long-haul (CSU) or short-haul (DSX-1) lines for T1 ...

  • Page 7

    ... DS2148 BLOCK DIAGRAM Figure 3-1 Unframed All Ones Insertion JACLK Jitter Attenuator MUX 2.048MHz to 1.544MHz PLL 16.384MHz or 8.192MHz or 4.096MHz or 2.048MHz BPCLK Synthesizer RPOS See Figure 3-2 RCLK RNEG PBEO MUX RCL/LOTC TPOS TCLK See Figure 3-3 TNEG HRST* TEST ...

  • Page 8

    RECEIVE LOGIC Figure 3-2 Clock Invert From Routed to Remote All Blocks CCR2.0 Loopback CCR2 Zero Detect 16 Zero Detect RIR1.7 RIR1.6 NRZ Data B8ZS/HDB3 Decoder BPV/CV/EXZ All Ones Loop Code Detector Detector CCR6.2/ RIR1.5 CCR6.0/ CCR6.1 ...

  • Page 9

    ... Routed to All Blocks 4. PIN DESCRIPTION The DS2148 can be controlled in a parallel port mode, a serial port mode hardware mode (Table 4-1, 4-2, and 4-3). The parallel and serial port modes are described in Section 3, and the hardware mode is described below. BUS INTERFACE SELECTION Table 4-1 BIS1 ...

  • Page 10

    ... PIN ASSIGNMENT IN PARALLEL PORT MODE Table 4-2a DS2148T DS2148G PIN # PIN ...

  • Page 11

    ... BIS0 = 1), serves as the data bus. In multiplexed bus operation (BIS1 = 0, BIS0 = 0), serves as an 8-bit multiplexed address/data bus. I Hardware Reset. Bringing HRST* low will reset the DS2148 setting all control bits to their default state of all zeros. O Interrupt [INT*] pin 23. Flags host controller during conditions and change of conditions defined in the Status Register ...

  • Page 12

    ACRONYM PIN I RCLK RD* 2 (DS*) RCL LOTC RNEG 39 O RPOS 38 O RTIP/ 27/ RRING 28 TCLK 43 TEST 26 TNEG 42 TPOS 41 TTIP/ 34/ O TRING 37 21 ...

  • Page 13

    ... PIN ASSIGNMENT IN SERIAL PORT MODE Table 4-3a DS2148T DS2148G PIN # PIN ...

  • Page 14

    ... PIN DESCRIPTIONS IN SERIAL PORT MODE (Sorted by Pin Name, DS2148T Pin Numbering) Table 4-3b ACRONYM PIN I/O BIS0/ 32/ BIS1 33 BPCLK 31 CS* 1 HRST ICES INT* 23 MCLK OCES 9 PBEO 24 RCLK 40 RCL/ 25 LOTC DESCRIPTION I Bus Interface Select Bits 0 & 1. Used to select bus interface option. See Table 4-1 for details. ...

  • Page 15

    ACRONYM PIN I RNEG RPOS 38 O RTIP/ 27/ RRING 28 5 SCLK SDI 6 SDO 7 O TCLK 43 TEST 26 TNEG 42 TPOS 41 TTIP/ 34/ O TRING VSM 20 V ...

  • Page 16

    ... PIN ASSIGNMENT IN HARDWARE MODE Table 4-4a DS2148T DS2148G PIN # PIN ...

  • Page 17

    ... PIN DESCRIPTIONS IN HARDWARE MODE (Sorted by Pin Name, DS2148T Pin Numbering) Table 4-4b ACRONYM PIN I/O BIS0/ 32/ BIS1 33 BPCLK 31 12 CES DJA 8 1 EGL ETS 2 HBE 11 HRST* 29 JAMUX 9 10 JAS L0/L1/ LOOP0/ 16/ LOOP1 17 DESCRIPTION I Bus Interface Select Bits 0 & 1. Used to select bus interface option. ...

  • Page 18

    ACRONYM PIN I/O MCLK 30 MM0/ 18/ MM1 NRZE PBEO RCLK RCL 25 O RNEG 39 O RPOS 38 O RT0/ 44/ RT1 23 RTIP/ 27/ RRING 28 4 SCLKE DESCRIPTION I ...

  • Page 19

    ACRONYM PIN I/O TCLK 43 TEST 26 TNEG 42 13 TPD TPOS 41 TTIP/ 34/ TRING 37 TX0/ 14/ TX1 15 21 VSM NOTES: 1) G.703 requires an accuracy of ±50ppm for ...

  • Page 20

    LOOP BACK CONTROL IN HARDWARE MODE Table 4-5 LOOPBACK SYMBOL Remote Loop Back Local Loop Back Analog Loop Back No Loop Back TRANSMIT DATA CONTROL IN HARDWARE MODE Table 4-6 TRANSMIT DATA Transmit Unframed All Ones Transmit Alternating Ones and ...

  • Page 21

    ... Operation 7 A4 (Note: tie all NA pins low SERIAL PORT MODE PINOUT (BIS1 = 1, BIS0 = 0) Figure 4 DS2148 5 SCLK Serial Port 6 SDI Operation 7 SDO (Note: tie all NA pins low) 8 ICES 9 OCES BIS1 33 tie low ...

  • Page 22

    ... HARDWARE MODE In hardware mode (BIS1 = 1, BIS0 = 1), pins 1-19, 23, 25, 31, and 44 are redefined to be used for initializing the DS2148. BPCLK (pin 31) defaults to a 16.384MHz output when in hardware mode. The RCL/LOTC (pin 25) is designated to RCL when in hardware mode. JABDS (CCR4.2) defaults to logic 0. The RHBE (CCR2.3) and THBE (CCR2.2) control bits are combined and controlled by HBE at pin 11 while the RSCLKE (CCR5 ...

  • Page 23

    Register Map REGISTER MAP Table 5-1 ACRONYM REGISTER NAME CCR1 Common Control Register 1 CCR2 Common Control Register 2 CCR3 Common Control Register 3 CCR4 Common Control Register 4 CCR5 Common Control Register 5 CCR6 Common Control Register 6 ...

  • Page 24

    ... Serial Port Operation Setting BIS1 = 1 and BIS0 = 0 enables the serial bus interface on the DS2148. Port read/write timing is unrelated to the system transmit and receive timing, allowing asynchronous reads or writes by the host. See Section 12 for the AC timing of the serial port. All serial port accesses are LSB first. See Figure 5-1, Figure 5-2, Figure 5-3, and Figure 5-4 for more details ...

  • Page 25

    SERIAL PORT OPERATION FOR READ ACCESS (R=1) MODE 1 Figure 5-1 ICES = 1 (sample SDI on the falling edge of SCLK) OCES = 1 (update SDO on rising edge of SCLK) SCLK CS* SDI A0 ...

  • Page 26

    SERIAL PORT OPERATION FOR READ ACCESS MODE 3 Figure 5-3 ICES = 0 (sample SDI on the rising edge of SCLK) OCES = 0 (update SDO on falling edge of SCLK) SCLK CS* SDI A0 A1 ...

  • Page 27

    SERIAL PORT OPERATION FOR WRITE ACCESS (R=0) Figure 5-5 MODES 1 and 2 ICES = 1 (sample SDI on the falling edge of SCLK) SCLK CS* SDI (lsb) WRITE ACCESS ENABLED SDO ...

  • Page 28

    CONTROL REGISTERS CCR1 (00H): COMMON CONTROL REGISTER 1 (MSB) ETS NRZE RCLA SYMBOL POSITION ETS CCR1.7 NRZE CCR1.6 RCLA CCR1.5 ECUE CCR1.4 JAMUX CCR1.3 TTOJ CCR1.2 TTOR CCR1.1 LOTCMC CCR1.0 ECUE JAMUX TTOJ DESCRIPTION E1/T1 Select ...

  • Page 29

    MCLK SELECTION Table 6-1 MCLK 2.048MHz 2.048MHz 1.544MHz CCR2 (01H): COMMON CONTROL REGISTER 2 (MSB) P25S N/A SCLD SYMBOL POSITION P25S CCR2.7 - CCR2.6 SCLD CCR2.5 CLDS CCR2.4 RHBE CCR2.3 THBE CCR2.2 TCES CCR2.1 RCES CCR2.0 JAMUX (CCR1. ...

  • Page 30

    CCR3 (02H): COMMON CONTROL REGISTER 3 (MSB) TUA1 ATUA1 TAOZ SYMBOL POSITION TUA1 CCR3.7 ATUA1 CCR3.6 TAOZ CCR3.5 TPRBSE CCR3.4 TLCE CCR3.3 LIRST CCR3.2 IBPV CCR3.1 IBE CCR3.0 TPRBSE TLCE LIRST DESCRIPTION Transmit Unframed All Ones. The polarity of this ...

  • Page 31

    ... CCR3.7 (TUA1 results in the LIU transmitting unframed all ones. After the power supplies have settled following power-up, initialize all control registers to the desired settings, then toggle the LIRST bit (CCR3.2). The DS2148 can be reset at anytime to the default settings by bringing HRST* (pin 29) low (level triggered powering down and powering up again. ...

  • Page 32

    CCR5 (04H): COMMON CONTROL REGISTER 5 (MSB) BPCS1 BPCS0 SYMBOL POSITION BPCS1 CCR5.7 BPCS0 CCR5.6 MM1 CCR5.5 MM0 CCR5.4 RSCLKE CCR5.3 TSCLKE CCR5.2 RT1 CCR5.1 RT0 CCR5.0 BACK PLANE CLOCK SELECT Table 6-3 BPCS1 (CCR5. MONITOR ...

  • Page 33

    MM1 (CCR5. MM0 INTERNAL LINEAR (CCR5.4) GAIN BOOST (dB) 0 Normal operation (no boost ...

  • Page 34

    ... Data in the receive path will act as normal while data presented at TPOS and TNEG will be ignored. See Figure 3-1 (DS2148 BLOCK DIAGRAM Figure 3-1 and section 8-2.1 for details loopback disabled 1 = loopback enabled Automatic Remote Loopback Enable and Reset ...

  • Page 35

    ... The user will always precede a read of any of the three status registers with a write. The byte written to the register will inform the DS2148 which bits the user wishes to read and have cleared. The user will write a byte to one of these registers with a one in the bit positions to be read and a zero in the other bit positions ...

  • Page 36

    RECEIVED ALARM CRITERIA Table 7-1 ALARM E1/T1 RUA1 E1 RUA1 T1 1 RCL E1 1 RCL T1 NOTES: 1) Receive carrier loss (RCL) is also known as loss-of-signal (LOS) or Red Alarm in T1. 2) See CCR1.5 for details. SR ...

  • Page 37

    IMR (07H): INTERRUPT MASK REGISTER (MSB) LUP LDN LOTC SYMBOL POSITION LUP IMR.7 LDN IMR.6 LOTC IMR.5 RUA1 IMR.4 RCL IMR.3 TCLE IMR.2 TOCD IMR.1 PRBSD IMR.0 RUA1 RCL TCLE DESCRIPTION Loop Up Code Detected interrupt masked 1 ...

  • Page 38

    RIR1 (08H): RECEIVE INFORMATION REGISTER 1 (MSB) ZD 16ZD SYMBOL POSITION ZD RIR1.7 (latched) 16ZD RIR1.6 (latched) HBD RIR1.5 (latched) RCLC RIR1.4 (latched) RUA1C RIR1.3 (latched) JALT RIR1.2 (latched) N/A RIR1.1 N/A RIR1.0 HBD RCLC RUA1C DESCRIPTION Zero Detect. Set ...

  • Page 39

    ... RCLK. It will be cleared when read. RL1 N/A ARLB RL0 Receive Level (dB) 0 < -2.5 1 -2.5 to -5.0 0 -5.0 to -7.5 1 -7.5 to -10.0 0 -10.0 to -12.5 1 -12.5 to -15.0 0 -15.0 to -17.5 1 -17.5 to -20.0 0 -20.0 to -22.5 1 -22.5 to -25.0 0 -25.0 to -27.5 1 -27.5 to -30.0 0 -30.0 to -32.5 1 -32.5 to -35.0 0 -35.0 to -37.5 1 > -37.5 DS2148/Q48 (LSB) SEC ...

  • Page 40

    ... In-Band Loop Code Generation and Detection The DS2148 has the ability to generate and detect a repeating bit pattern that is from one to eight or sixteen bits in length. To transmit a pattern, the user will load the pattern to be sent into the Transmit Code Definition (TCD1 and TCD2) registers and select the proper length of the pattern by setting the TC0 and TC1 bits in the In-Band Code Control (IBCC) register ...

  • Page 41

    TRANSMIT CODE LENGTH Table 8-1 TC1 RECEIVE CODE LENGTH Table 8-2 RUP2/ RDN2 RUP1/ RDN1 TCD1 (0BH): TRANSMIT CODE DEFINITION REGISTER 1 (MSB SYMBOL POSITION C7 ...

  • Page 42

    TCD2 (0CH): TRANSMIT CODE DEFINITION REGISTER 2 (MSB) C15 C14 SYMBOL POSITION C15 TCD2.7 C14 TCD2.6 C13 TCD2.5 C12 TCD2.4 C11 TCD2.3 C10 TCD2.2 C9 TCD2.1 C8 TCD2.0 RUPCD1 (0DH): RECEIVE UP CODE DEFINITION REGISTER 1 (MSB SYMBOL ...

  • Page 43

    RUPCD2 (0EH): RECEIVE UP CODE DEFINITION REGISTER 2 (MSB) C15 C14 SYMBOL POSITION C15 RUPCD2.7 C14 RUPCD2.6 C13 RUPCD2.5 C12 RUPCD2.4 C11 RUPCD2.3 C10 RUPCD2.2 C9 RUPCD2.1 C8 RUPCD2.0 RDNCD1 (0FH): RECEIVE DOWN CODE DEFINITION REGISTER 1 (MSB ...

  • Page 44

    ... ARLB. 8.2.2 Local Loopback (LLB) When LLB (CCR6.7) is set to a one, the DS2148 is placed into local loopback. In this loopback, data on the transmit-side will continue to be transmitted as normal. TCLK and TPOS/TNEG will pass through the jitter attenuator (if enabled) and be output at RCLK and RPOS/RNEG. Incoming data from the line at RTIP and RRING will be ignored ...

  • Page 45

    ... Analog Loopback (ALB) Setting ALB (CCR6. one puts the DS2148 in Analog Loop Back. Signals at TTIP and TRING will be internally connected to RTIP and RRING. The incoming signals at RTIP and RRING will be ignored. The signals at TTIP and TRING will be transmitted as normal. (See Figure 3-1.) 8 ...

  • Page 46

    ... ECUE must be set back to zero and another transition must occur for subsequent reads/resets of the ECR registers. Note that the DS2148 can report errors at RNEG when in NRZ mode (CCR1 outputting a pulse for each error occurrence. The counter saturates at 65,535 and will not rollover ...

  • Page 47

    ... BPCLK. In hardware mode, BPCLK defaults to a 16.384MHz output. The DS2148 has a bypass mode for the receive side clock and data. This allows the BPCLK to be derived from RCLK after the jitter attenuator while the clock and data presented at RCLK, RPOS, and RNEG go unaltered ...

  • Page 48

    ... Jitter Attenuator The DS2148 contains an onboard jitter attenuator that can be set to a depth of either 32 bits or 128 bits via the JABDS bit (CCR4.2). In hardware mode the depth is 128 bits and cannot be changed. The 128-bit mode is used in applications where large excursions of wander are expected. The 32-bit mode is used in delay sensitive applications ...

  • Page 49

    ... G.703 Synchronization Signal The DS2148 is capable of receiving a 2.048MHz square-wave synchronization clock as specified in section 13 of ITU G.703 (10/98). To use the DS2148 in this mode, set the receive synchronization clock enable (CCR5. The DS2148 can also transmit the 2.048MHz square-wave synchronization clock as specified in Section 10 of G.703. To transmit the 2.048MHz clock, set the transmit synchronization clock enable (CCR5 ...

  • Page 50

    TRANSFORMER SPECIFICATIONS FOR 5V OPERATION Table 9-3 SPECIFICATION Turns Ratio 5V Applications Primary Inductance Leakage Inductance Interwinding Capacitance Transmit Transformer DC Resistance Primary (Device Side) Secondary Receive Transformer DC Resistance Primary (Device Side) Secondary RECOMMENDED VALUE 1:1(receive) and 1:1.36(transmit) ±2% ...

  • Page 51

    ... When this feature is disabled 37.5W for 75W, 60W for 120W E1 systems, or 50W for 100W T1 lines. 4) See Table 9-1 and Table 9-2 for the appropriate transmit transformer turns ratio (N). Rt TTIP 0.47µF (non polarized) TRING Rt RTIP RRING Rr Rr 0.1µ DS2148 +V DD 0.1µF V (21 (22) SS 10µF 0.01µF 0.1µF V (36) DD ...

  • Page 52

    ... The Rt resistors are used to increase the transmitter return loss (Table 9-1). No return loss is required for T1 applications. 8) The transmit transformer turns ratio (N) would be 1:1.36 for 5V operation. 9) The 68mF is used to keep the local power plane potential within tolerance during a surge. +VDD DS2148 TTIP 0.47uF ...

  • Page 53

    ... The 68mF is used to keep the local power plane potential within tolerance during a surge TTIP 0.47µF S (non- C1 polarized) TRING 470 RTIP RRING 470 Rr Rr 0.1µ DS2148 +V DD 0.1µF V (21 (22) SS 10µF 0.01µF V (36) DD 0.1µF V (35) SS 10µF MCLK 2.048MHz (this clock can also be 1.544MHz for T1 only applications) 68µ ...

  • Page 54

    E1 TRANSMIT PULSE TEMPLATE Figure 9-4 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -250 -200 194ns 219ns -150 -100 - TIME (ns 269ns G.703 Template 100 150 ...

  • Page 55

    T1 TRANSMIT PULSE TEMPLATE Figure 9-5 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 T1.102/87, T1.403, -0.2 CB 119 (Oct. 79), & I.431 Template -0.3 -0.4 -0.5 -500 -400 -300 -200 MAXIMUM CURVE UI ...

  • Page 56

    ... JITTER TOLERANCE Figure 9-6 1K 100 TR 62411 (Dec. 90) 10 ITU-T G.823 1 0 JITTER ATTENUATION Figure 9-7 0dB -20dB E1 -40dB -60dB 1 10 DS2148 Tolerance 100 1K 10K FREQUENCY (Hz) ITU G.7XX TBR12 Prohibited Area Prohibited Area T1 TR 62411 (Dec. 90) Prohibited Area 100 1K 10K FREQUENCY (Hz 100K ...

  • Page 57

    ... DS21Q48 QUAD LIU The DS21Q48 is a quad version of the DS2148G utilizing CABGA on carrier packaging technology. The four LIUs are controlled via the parallel port mode. Serial and hardware modes are unavailable in this package. DS21Q48 PIN ASSIGNMENT Table 10-1 DS21Q48 I/O PIN ...

  • Page 58

    DS21Q48 I/O PIN A10 B11 F10 A11 ...

  • Page 59

    DS21Q48 I/O PIN L10 - PARALLEL PORT MODE V DD1 ...

  • Page 60

    BGA PIN LAYOUT Figure 10 RTIP TTIP RRING TRING VSS VDD CS RPOS RNEG D3 ...

  • Page 61

    ... DC CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS* Voltage Range on Any Pin Relative to Ground Operating Temperature Range for DS2148TN Storage Temperature Range * This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability ...

  • Page 62

    THERMAL CHARACTERISTICS OF DS21Q48 BGA PACKAGE PARAMETER Ambient Temperature Junction Temperature Theta-JA (θ Still Air JA Theta-JC (θ Still Air JC NOTES: 1) The package is mounted on a four-layer JEDEC-standard test board. 2) Theta-JA (θ ...

  • Page 63

    AC CHARACTERISTICS AC CHARACTERISTICS—MULTIPLEXED PARALLEL PORT (BIS1 = 0, BIS0 = 0) PARAMETER Cycle Time Pulse Width, DS Low or RD* High Pulse Width, DS High or RD* Low Input Rise/Fall times R/W* Hold Time R/W* Setup Time Before ...

  • Page 64

    INTEL BUS READ TIMING (PBTS = 0, BIS1 = 0, BIS0 = 0) Figure 12-1 ALE t ASD WR* RD* PW CS* AD0-AD7 INTEL BUS WRITE TIMING (PBTS = 0, BIS1 = 0, BIS0 = 0) Figure 12-2 ALE t ...

  • Page 65

    MOTOROLA BUS TIMING (PBTS = 1, BIS1 = 0, BIS0 = 0) Figure 12 ASD R/W* t AD0-AD7 (read) CS* AD0-AD7 (write) PW ASH t ASED t CYC t RWS t DDR ASL t AHL ...

  • Page 66

    AC CHARACTERISTICS—NONMULTIPLEXED PARALLEL PORT (BIS1 = 0, BIS0 = 1) PARAMETER Setup Time for A0 to A4, Valid to CS* Active Setup Time for CS* Active to Either RD*, WR*, or DS* Active Delay Time From Either RD* or DS* ...

  • Page 67

    INTEL BUS READ TIMING (PBTS = 0, BIS1 = 0, BIS0 = 1) Figure12 WR* t1 CS* 0ns min. RD* INTEL BUS WRITE TIMING (PBTS = 0, BIS1 = 0, BIS0 = 1) Figure ...

  • Page 68

    MOTOROLA BUS READ TIMING (PBTS = 1, BIS1 = 0, BIS0 = 1) Figure 12 R/W* t1 CS* 0ns min. DS* MOTOROLA BUS WRITE TIMING (PBTS = 1, BIS1 = 0, BIS0 = 1) ...

  • Page 69

    AC CHARACTERISTICS—SERIAL PORT (BIS1 = 1, BIS0 = 0) PARAMETER Setup Time CS* to SCLK Setup Time SDI to SCLK Hold Time SCLK to SDI SCLK High/Low Time SCLK Rise/Fall Time SCLK to CS* Inactive CS* Inactive Time SCLK to ...

  • Page 70

    AC CHARACTERISTICS—RECEIVE SIDE PARAMETER RCLK Period RCLK Pulse Width RCLK Pulse Width Delay RCLK to RPOS, RNEG, PBEO, RBPV Valid NOTES Mode Mode. 3) Jitter attenuator enabled in the receive path. 4) Jitter attenuator ...

  • Page 71

    AC CHARACTERISTICS—TRANSMIT SIDE (-40°C to +85°C; V PARAMETER TCLK Period TCLK Pulse Width TPOS/TNEG Setup to TCLK Falling or Rising TPOS/TNEG Hold From TCLK Falling or Rising TCLK Rise and Fall Times See Figure 12-10 NOTES Mode. 2) ...

  • Page 72

    MECHANICAL DIMENSIONS SEE DETAIL "A" SUGGESTED PAD LAYOUT 44 PIN TQFP, 10*10*1.0 DIMENSIONS ARE IN MILLIMETERS ...

  • Page 73

    ...

  • Page 74

    Mechanical Dimensions—Quad Version 17 TOP VIEW (DIE SIDE) 2.60 REF Z 1.27 13.97 0.20 1.52 4 DETAIL A 0.76 DETAIL B SIDE VIEW ...

  • Page 75

    LABEL THICKNESS 2.60 REF 0.76 REF SOLDER BALL f 0.76 REF f 0.76 f 0.76 DETAIL A SEATING PLANE DETAIL 0. 0. ...