DS2148 Dallas Semiconducotr, DS2148 Datasheet - Page 17

• Manufacturer Part Number: DS2148
• Description: 5V E1/T1/J1 Line Interface
• Manufacturer: Dallas Semiconducotr

PIN DESCRIPTIONS IN HARDWARE MODE (Sorted by Pin Name, DS2148T Pin
Numbering) Table 4-4b
ACRONYM
L0/L1/L2
JAMUX
LOOP0/
BPCLK
LOOP1
HRST*
BIS0/
BIS1
HBE
EGL
CES
DJA
ETS
JAS
PIN
32/
16/
33
12
11
29
10
17
31
7/
6/
8
1
2
9
5
I/O
O
I
I
I
I
I
I
I
I
I
I
I
DESCRIPTION
Bus Interface Select Bits 0 & 1. Used to select bus interface option.
BIS0 = 1 and BIS1 = 1 selects hardware mode.
Back Plane Clock. 16.384 MHz output.
Receive & Transmit Clock Edge Select. Selects which RCLK
edge to update RPOS and RNEG and which TCLK edge to sample
TPOS and TNEG.
0 = update RNEG/RPOS on rising edge of RCLK; sample
TPOS/TNEG on falling edge of TCLK
1 = update RNEG/RPOS on falling edge of RCLK; sample
TPOS/TNEG on rising edge of TCLK
Disable Jitter Attenuator.
0 = jitter attenuator enabled
1 = jitter attenuator disabled
Receive Equalizer Gain Limit. This pin controls the sensitivity of
the receive equalizer.
EGL E1 (ETS = 0)
0 = -12dB (short haul)
1 = -43dB (long haul)
EGL
0 = -36dB (long haul)
1 = -30dB (limited long haul)
E1/T1 Select.
0 = E1
1 = T1
Receive & Transmit HDB3/B8ZS Enable.
0 = enable HDB3 (E1)/B8ZS (T1)
1 = disable HDB3 (E1)/B8ZS (T1)
Hardware Reset. Bringing HRST* low will reset the DS2148.
Jitter Attenuator MUX. Controls the source for JACLK. See
Figure 3-1 and Table 4-10.
MCLK = 2.048 MHz
MCLK = 2.048 MHz
MCLK = 1.544 MHz
Jitter Attenuator Select.
0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
Transmit LIU Waveshape Select Bits 0 & 1 [H/W Mode]. These
inputs determine the waveshape of the transmitter. See Table 9-1
and Table 9-2.
Loopback Select Bits 0 & 1 [H/W Mode]. These inputs determine
the active loopback mode (if any). See Table 4-5.
E1 (ETS = 0)
T1 (ETS = 1)
T1 (ETS = 1)
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JAMUX
0
1
0