DS2148 Dallas Semiconducotr, DS2148 Datasheet - Page 31

• Manufacturer Part Number: DS2148
• Description: 5V E1/T1/J1 Line Interface
• Manufacturer: Dallas Semiconducotr

6.1
The DS2148 will reset itself upon power-up, setting all writeable registers to 00h and clearing the status
and information registers. CCR3.7 (TUA1) = 0 results in the LIU transmitting unframed all ones. After
the power supplies have settled following power-up, initialize all control registers to the desired settings,
then toggle the LIRST bit (CCR3.2). The DS2148 can be reset at anytime to the default settings by
bringing HRST* (pin 29) low (level triggered) or by powering down and powering up again.
CCR4 (03H): COMMON CONTROL REGISTER 4
RECEIVE SENSITIVITY SETTINGS Table 6-2
(MSB)
SYMBOL
L2
JABDS
EGL
TPD
DJA
JAS
Device Power-Up And Reset
L2
L1
L0
(CCR4.4)
EGL
0
1
1
0
L1
POSITION
CCR4.7
CCR4.6
CCR4.5
CCR4.4
CCR4.3
CCR4.2
CCR4.1
CCR4.0
L0
DESCRIPTION
Line Build Out Select Bit 2. Sets the transmitter build out
(Table 9-1 for E1 and Table 9-2 for T1)
Line Build Out Select Bit 1. Sets the transmitter build out
(Table 9-1 for E1 and Table 9-2 for T1)
Line Build Out Select Bit 0. Sets the transmitter build out
(Table 9-1 for E1 and Table 9-2 for T1)
Receive Equalizer Gain Limit. This bit controls the sensitivity
of the receive equalizer (Table 6-2)
Jitter Attenuator Select.
0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
Jitter Attenuator Buffer Depth Select.
0 = 128 bits
1 = 32 bits (use for delay sensitive applications)
Disable Jitter Attenuator.
0 = jitter attenuator enabled
1 = jitter attenuator disabled
Transmit Power-Down.
0 = normal transmitter operation
1 = powers down the transmitter and 3-states the TTIP and
TRING pins
(CCR1.7)
0 (E1)
0 (E1)
1 (T1)
1 (T1)
EGL
ETS
31 of 75
JAS
-12dB (short haul)
-43dB (long haul)
-30dB (limited long haul)
-36dB (long haul)
RECEIVE SENSITIVITY
JABDS
DJA
(LSB)
TPD