IRCC SMSC Corporation, IRCC Datasheet - Page 35

• Manufacturer Part Number: IRCC
• Description: INFRARED COMMUNICATIONS CONTROLLER
• Manufacturer: SMSC Corporation

When the No Wait bit is one, the ISA Bus
nSRDY signal goes active following the trailing
edge of the ISA I/O command and inactive
following the rising edge (see Zero Wait State
Support).
String Move, Bit 2
When
programmed I/O host interface is qualified by
IOCHRDY (Table 23). See IOCHRDY Time-Out.
DMA Burst Mode, bit 1
When the DMA Burst Mode bit is one, DMA
Burst (Demand) mode is enabled.
FIFO Threshold Register (Address 2)
The FIFO Threshold Register contains the
programmable FIFO threshold count. The FIFO
Threshold is programmable from 0 to 127. Bit 7
in the FIFO Threshold register is read-only and
will always return zero. FIFO Threshold values
the
STRING
String
MOVE
X
X
0
1
Move
BURST
DMA
X
X
0
1
bit
is
Table 23 - I/O Interface Modes
ENABLE
DMA
When the
one,
0
0
1
1
the
Programmed I/O, no IOCHRDY
Programmed I/O, uses IOCHRDY
Single Byte DMA Mode
Demand Mode DMA
35
mode is enabled (Table 23).
DMA Enable, bit 0
DMA Enable is connected to a signal in the
Interface Description called DMAEN that is used
by the chip-level interface to tristate the IrCC
DMA controls when the DMA interface is
inactive. When the DMA Enable bit is one, the
DMA host interface is active (Table 23). When
the DMA Enable bit is zero (default), the nDACK
and TC inputs are disabled and DRQ output is
gated off.
typically reflect the overall I/O performance
characteristics of the host; the lower the value,
the longer the interval between service requests
and the faster the host must be to successfully
service them. The same threshold value can be
used for both I/O read and I/O write cases.
FUNCTION