IRCC SMSC Corporation, IRCC Datasheet - Page 6

• Manufacturer Part Number: IRCC
• Description: INFRARED COMMUNICATIONS CONTROLLER
• Manufacturer: SMSC Corporation

DMAEN
DMAEN is used by the chip-level interface to
tristate the IrCC DRQ output when the DMA
Enable bit is inactive. The DMA Enable bit is
located in SCE Configuration Register B, bit 0.
IRQEN
IRQEN is used by the chip-level interface to
tristate the IrCC IRQ output when the OUT2 bit is
inactive.
MODEM Control Register.
Power Down
The Power Down pin is used by the chip-level
interface to put the SCE into low power mode.
NOTE: Power Down does not force the ACE550
into low power mode.
Power Down
DMAEN
RESET
IRQEN
NAME
The OUT2 bit is located in 16550A
nACE
nSCE
VCC
GND
CLK
SIZE (BITS)
1
1
1
1
1
1
1
Output
Output
Power
Power
TYPE
Input
Input
Input
Input
Input
6
CHIP-LEVEL CONFIGURATION CONTROLS
The following signals come from chip-level
configuration registers. There are two types of
Chip-Level Configuration Controls: IrCC-Specific
controls, and Legacy Controls. Both types have
equivalent controls in either the IrCC ACE or
SCE Registers.
The IrCC-Specific controls have been newly
added primarily to support the IrCC block.
Provisions have been made in new chip-level
configuraton contexts to accommodate these
signals.
The Legacy controls already exist in other
contexts. Provisions have been made in legacy
devices to accommodate these controls from
either the Chip-Level Configuration Registers or
the IrCC Registers; i.e., the last updated value
from either source determines the current control
state and is visible in both registers.
ACE 550 Register Bank Select
SCE Register Bank Select
DRQ Tristate Control
IRQ Tristate Control
IrCC System Reset
Low Power Control
System Ground
DESCRIPTION
System Supply
System Clock