IRCC SMSC Corporation, IRCC Datasheet - Page 68

• Manufacturer Part Number: IRCC
• Description: INFRARED COMMUNICATIONS CONTROLLER
• Manufacturer: SMSC Corporation

DMA Burst mode is enabled by setting the DMA
Burst bit in SCE Configuration Register B.
Demand Mode DMA transfers up to 32 data
32 I/Ox Clock DMA Refresh Counter
The 32 I/Ox Clock DMA Refresh Counter is used
to prevent DRQ from staying active for more than
32 I/O read/write cycles at a time.
The counter is stopped and preloaded whenever
DRQ is not active. Once DRQ becomes active,
the counter decrements until zero-count or DRQ
is deactived.
D M A E n a b l e
D M A B u r s t
FIGURE 37 - DMA BURST MODE TIMING
n D A C K
D R Q
A E N
I / O x
T C
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guarantees that DRQ relinquishes the ISA bus
after thirty-two DMA I/O read or write cycles to
allow for memory refresh.
In Demand Mode, the count-zero condition
always clears DRQ and triggers a Refresh
Interval. The Refresh Interval remains active for
350ns following an inactive nDACK (Figure 38).
If there is more data to transfer, DRQ goes active
again and the cycle repeats.
Single Byte Mode DMA does not use the 32 I/Ox
Clock Refresh Counter.